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- Publisher
- Wiley
- Copyright
- Copyright © 2015 John Wiley & Sons, Ltd.
- ISSN
- 0098-9886
- eISSN
- 1097-007X
- DOI
- 10.1002/cta.1972
- Publisher site
- See Article on Publisher Site
Abstract
Summary The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.
Journal
International Journal of Circuit Theory and Applications – Wiley
Published: Jun 1, 2015