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A low-noise high-precision analog front end system for biopotential signals recording application

A low-noise high-precision analog front end system for biopotential signals recording application A high precision and low noise analog front end system is proposed in this paper for recording biopotential signals. The system consists of a capacitor-coupled chopper instrument amplifier (CCIA) and a continue-time (CT) ΔƩ analog to digital converter (ADC). In order to avoid off-chip low-noise reference, a chopper bias circuit is employed to provide low noise bias for CCIA. A positive feedback loop improves the input impedance of CCIA, and a ripple reduction loop based active integrator eliminates the ripple caused by chopping. A new switch-capacitor integrator is employed in the DC servo loop (DSL) to suppress electrode DC offset and save the integrator capacitor area. The CTΔƩ modulator employs an energy-efficient 2nd-order structure consisting of a cascade of integrators with feedforward topology, which is unconditionally stable. The CCIA in the proposed analog front end system achieves an input-referred noise of 1.36 μVrms (0.5−100 Hz), and the CTΔƩ ADC achieves a signal noise distortion ratio (SNDR) of 96.2 dB, which are state of the art. The analog front end system is simulated using the standard 0.18 µm CMOS process, and the total power consumption with a 1.8 V supply is less than 112.5 µW. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Analog Integrated Circuits and Signal Processing Springer Journals

A low-noise high-precision analog front end system for biopotential signals recording application

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References (20)

Publisher
Springer Journals
Copyright
Copyright © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022
ISSN
0925-1030
eISSN
1573-1979
DOI
10.1007/s10470-022-01991-7
Publisher site
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Abstract

A high precision and low noise analog front end system is proposed in this paper for recording biopotential signals. The system consists of a capacitor-coupled chopper instrument amplifier (CCIA) and a continue-time (CT) ΔƩ analog to digital converter (ADC). In order to avoid off-chip low-noise reference, a chopper bias circuit is employed to provide low noise bias for CCIA. A positive feedback loop improves the input impedance of CCIA, and a ripple reduction loop based active integrator eliminates the ripple caused by chopping. A new switch-capacitor integrator is employed in the DC servo loop (DSL) to suppress electrode DC offset and save the integrator capacitor area. The CTΔƩ modulator employs an energy-efficient 2nd-order structure consisting of a cascade of integrators with feedforward topology, which is unconditionally stable. The CCIA in the proposed analog front end system achieves an input-referred noise of 1.36 μVrms (0.5−100 Hz), and the CTΔƩ ADC achieves a signal noise distortion ratio (SNDR) of 96.2 dB, which are state of the art. The analog front end system is simulated using the standard 0.18 µm CMOS process, and the total power consumption with a 1.8 V supply is less than 112.5 µW.

Journal

Analog Integrated Circuits and Signal Processing – Springer Journals

Published: Apr 1, 2022

Keywords: Analog front end; Capacitor-coupled chopper instrument amplifier (CCIA); Continue-time (CT) ΔƩ ADC; Ripple reduction loop (RRL); DC servo loop (DSL)

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