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Manufacturing 100‐µm‐thick silicon solar cells with efficiencies greater than 20% in a pilot production line

Manufacturing 100‐µm‐thick silicon solar cells with efficiencies greater than 20% in a pilot... Reducing wafer thickness while increasing power conversion efficiency is the most effective way to reduce cost per Watt of a silicon photovoltaic module. Within the European project 20 percent efficiency on less than 100‐µm‐thick, industrially feasible crystalline silicon solar cells (“20plµs”), we study the whole process chain for thin wafers, from wafering to module integration and life‐cycle analysis. We investigate three different solar cell fabrication routes, categorized according to the temperature of the junction formation process and the wafer doping type: p‐type silicon high temperature, n‐type silicon high temperature and n‐type silicon low temperature. For each route, an efficiency of 19.5% or greater is achieved on wafers less than 100 µm thick, with a maximum efficiency of 21.1% on an 80‐µm‐thick wafer. The n‐type high temperature route is then transferred to a pilot production line, and a median solar cell efficiency of 20.0% is demonstrated on 100‐µm‐thick wafers. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Physica Status Solidi (A) Applications and Materials Science Wiley

Manufacturing 100‐µm‐thick silicon solar cells with efficiencies greater than 20% in a pilot production line

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References (25)

Publisher
Wiley
Copyright
"© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim"
ISSN
1862-6300
eISSN
1862-6319
DOI
10.1002/pssa.201431241
Publisher site
See Article on Publisher Site

Abstract

Reducing wafer thickness while increasing power conversion efficiency is the most effective way to reduce cost per Watt of a silicon photovoltaic module. Within the European project 20 percent efficiency on less than 100‐µm‐thick, industrially feasible crystalline silicon solar cells (“20plµs”), we study the whole process chain for thin wafers, from wafering to module integration and life‐cycle analysis. We investigate three different solar cell fabrication routes, categorized according to the temperature of the junction formation process and the wafer doping type: p‐type silicon high temperature, n‐type silicon high temperature and n‐type silicon low temperature. For each route, an efficiency of 19.5% or greater is achieved on wafers less than 100 µm thick, with a maximum efficiency of 21.1% on an 80‐µm‐thick wafer. The n‐type high temperature route is then transferred to a pilot production line, and a median solar cell efficiency of 20.0% is demonstrated on 100‐µm‐thick wafers.

Journal

Physica Status Solidi (A) Applications and Materials Science – Wiley

Published: Jan 1, 2015

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