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A low-overhead coherence solution for multiprocessors with private cache memories

A low-overhead coherence solution for multiprocessors with private cache memories This paper presents a cache coherence solution for multiprocessors organized around a single time-shared bus. The solution aims at reducing bus traffic and hence bus wait time. This in turn increases the overall processor utilization. Unlike most traditional high-performance coherence solutions, this solution does not use any global tables. Furthermore, this coherence scheme is modular and easily extensible, requiring no modification of cache modules to add more processors to a system. The performance of this scheme is evaluated by using an approximate analysis method. It is shown that the performance of this scheme is closely tied with the miss ratio and the amount of sharing between processors. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGARCH Computer Architecture News Association for Computing Machinery

A low-overhead coherence solution for multiprocessors with private cache memories

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References (8)

Publisher
Association for Computing Machinery
Copyright
Copyright © 1984 by ACM Inc.
ISSN
0163-5964
DOI
10.1145/773453.808204
Publisher site
See Article on Publisher Site

Abstract

This paper presents a cache coherence solution for multiprocessors organized around a single time-shared bus. The solution aims at reducing bus traffic and hence bus wait time. This in turn increases the overall processor utilization. Unlike most traditional high-performance coherence solutions, this solution does not use any global tables. Furthermore, this coherence scheme is modular and easily extensible, requiring no modification of cache modules to add more processors to a system. The performance of this scheme is evaluated by using an approximate analysis method. It is shown that the performance of this scheme is closely tied with the miss ratio and the amount of sharing between processors.

Journal

ACM SIGARCH Computer Architecture NewsAssociation for Computing Machinery

Published: Jun 1, 1984

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