Low‐power, latch‐based multistage time‐to‐digital converter
in 65 nm CMOS technology
In this paper, a low‐power and high‐resolution latch‐based time‐to‐digital converter (TDC) based on a multistage
scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new
design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new
design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads.
high resolution, low power, TDC, VLSI
1 | INTRODUCTION
High‐precision time interval measurement is highly significant in many systems. Time‐to‐digital converter (TDC) is a
system of time measurement, which converts the interval between 2 input pulses into a digital code. Time‐to‐digital
converter has numerous applications, such as phase failure detection in the design of phase‐locked loops.
of TDCs instead of phase comparator in phase‐locked loop structure leads to removal of analog parts such as charge
pump and loop filter. In addition, TDC is used in the structure of time‐based analog to digital converters.
In this type
of analog‐to‐digital converters, analog input voltage is turned into a time interval, and then the time interval is converted
to a digital code through TDC. Also, TDC is used in medical imaging systems such as scanners,
other time of flight
and coupled with single photon avalanche diode array to build complementary metal oxide
semiconductor image sensor.
A basic structure in design of TDC is flash TDC, which is composed of a delay line with several stages of buffers and
In this TDC, resolution is equal to delay of each buffer, which is the long delay. To enhance resolution,
Vernier delay line structure was used.
The structure of this TDC is shown in Figure 1. This TDC is made up of several
stages; each stage includes 2 different delay lines and a comparator. Resolution can be less than the delay of a buffer
(resolution equivalent of difference in delay of 2 delay cells). In this structure, dynamic range is limited to the number
of stages, and by adding extra stages, the dynamic range is increased. Because each stage is made up of 2 buffers and a
comparator, power consumption of the circuit increases significantly. In addition, its linearity reduces as the number of
stages increases. Two‐dimensional Vernier TDC proposed in Vercesi et al
reduced the length of the delay lines to
increase the efficiency compared with Vernier delay line TDC. However, this TDC had limited dynamic range and
had serious problem in linearity. Three‐dimensional Vernier space TDC
was introduced to increase dynamic range
with minimizing the delay line. Vernier Ring TDC proposed in Yu et al
places the Vernier delay cells and arbiters in
a ring format and reuses them for the measurement of the input time interval. This TDC achieves larger detectable range
and fine time resolution, but has higher power consumption. Gated‐Vernier TDC, which has 2 gated ring oscillators, acts
as the delay lines in an improved Vernier TDC.
This TDC improves the trade‐off between the time resolution and the
absolute delay of gated ring oscillator stages.
Another structure for increasing TDC resolution is the multistage TDC.
In such TDC, a coarse stage with high
dynamic range and fine stage with high resolution will be considered. Multistage TDC can use the time amplifier, which
amplifies the residue time after the coarse stage and transfers it to the fine stage. Although this structure is used for
increasing resolution, it has poor linearity and dissipates extra power, because of using time amplifier. In addition,
considering the fact that time amplifier is usually analog, it reduces stability of circuit against noise. Subexponent
TDC proposed in Kim et al
consists of a conventional integer TDC for integer‐level time difference and a subexponent
TDC, which generates the exponent‐only information for fractional time difference to have wide input range and fine
resolution. Compact algorithmic TDC
has used the cyclic comparison algorithm and time amplifier to receive fine
Received: 21 May 2017 Revised: 12 February 2018 Accepted: 18 February 2018
1264 Copyright © 2018 John Wiley & Sons, Ltd. Int J Circ Theor Appl. 2018;46:1264–1271.wileyonlinelibrary.com/journal/cta