Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology

Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology In this paper, a low‐power and high‐resolution latch‐based time‐to‐digital converter (TDC) based on a multistage scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png International Journal of Circuit Theory and Applications Wiley

Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology

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Publisher
Wiley
Copyright
Copyright © 2018 John Wiley & Sons, Ltd.
ISSN
0098-9886
eISSN
1097-007X
D.O.I.
10.1002/cta.2468
Publisher site
See Article on Publisher Site

Abstract

In this paper, a low‐power and high‐resolution latch‐based time‐to‐digital converter (TDC) based on a multistage scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads.

Journal

International Journal of Circuit Theory and ApplicationsWiley

Published: Jan 1, 2018

Keywords: ; ; ;

References

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