Impact of the RT‐level architecture on the power performance of tunnel transistor circuits

Impact of the RT‐level architecture on the power performance of tunnel transistor circuits Tunnel field‐effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer–level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png International Journal of Circuit Theory and Applications Wiley

Impact of the RT‐level architecture on the power performance of tunnel transistor circuits

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Publisher
Wiley Subscription Services, Inc., A Wiley Company
Copyright
Copyright © 2018 John Wiley & Sons, Ltd.
ISSN
0098-9886
eISSN
1097-007X
D.O.I.
10.1002/cta.2398
Publisher site
See Article on Publisher Site

Abstract

Tunnel field‐effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer–level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.

Journal

International Journal of Circuit Theory and ApplicationsWiley

Published: Jan 1, 2018

Keywords: ; ; ; ; ;

References

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