Impact of the RT‐level architecture on the power
performance of tunnel transistor circuits
María J. Avedillo | Juan Núñez
Instituto de Microelectrónica de Sevilla,
IMSE‐CNM (CSIC/Universidad de
Sevilla), Sevilla, Spain
Juan Núñez, Instituto de Microelectrónica
de Sevilla, IMSE‐CNM (CSIC/Universidad
de Sevilla), Sevilla, Spain.
Tunnel field‐effect transistors (TFETs) are one of the most attractive steep
subthreshold slope devices currently being investigated as a means of
overcoming the power density and energy inefficiency limitations of
Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper,
we analyze the relationship between devices and register transfer–level
architecture choices. We claim that architectural issues should be considered
when evaluating this type of transistors because of the differences in delay versus
supply voltage behavior exhibited by TFET logic gates with respect to CMOS
gates. More specifically, the potential of pipelining and parallelism, both of
which rely on lowering supply voltage, as power reduction techniques is
evaluated and compared for CMOS and TFET technologies. The results obtained
show significantly larger savings in power and energy per clock cycle for the
TFET designs than for their CMOS counterparts, especially at low voltages.
Pipelining and parallelism make it possibly to fully exploit the distinguishing
characteristics of TFETs, and their relevance as competitive TFET circuit design
solutions should be explored in greater depth.
concurrency, low power, parallelism, pipelining, steep subthreshold slope, tunnel transistors
1 | INTRODUCTION
Intensive research is currently being conducted into devices with steeper subthreshold slopes (SS) below the physical
limit of 60 mV/dec of CMOS technologies. A smaller SS makes it possible to lower threshold voltage while keeping
leakage current under control, facilitating low‐voltage operation with acceptable speed, and thus overcoming the power
density problems and energy inefficiency of scaled CMOS.
Tunnel transistors (TFETs) are one of the most attractive steep subthreshold slope devices.
with SS under 60 mV/dec have already been obtained in different material systems, including silicon TFETs and III‐V
TFETs. Band‐to‐band TFETs based on two‐dimensional transition metal dichalcogenide semiconductors are being
explored as a potential means of improving their own currents (I
Many benchmarking efforts have been made to evaluate gains over CMOS and, thereby, identify those devices that
are the most promising candidates for replacing or complementing CMOS under different metrics or in different
application areas. Several works have shown power benefits for iso‐performance or higher performance at iso‐power
up to moderate operating frequencies.
This is due to the fact that current TFETs do not reach the on‐current values
Received: 21 March 2017 Revised: 27 July 2017 Accepted: 10 August 2017
Int J Circ Theor Appl. 2018;46:647–655. Copyright © 2017 John Wiley & Sons, Ltd.wileyonlinelibrary.com/journal/cta 647