In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.
International Journal of Circuit Theory and Applications – Wiley
Published: Jan 1, 2018
Keywords: ; ; ; ;
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