A systematic approach to designing a wide‐current range, MOS capacitor‐based switched‐capacitor DC‐DC converter with an augmenting LDO

A systematic approach to designing a wide‐current range, MOS capacitor‐based... Switched‐capacitor DC‐DC converters (SC DC‐DC) are analyzed for loss sources, voltage regulation integrity, start‐up latency, and ripple size, while the trade‐offs between these metrics are derived. These analyses are used to design a SC DC‐DC that achieves high efficiency in a wide load current range. Four‐way interleaving was employed to reduce the output ripple and efficiency loss due to this ripple. The design can be reconfigured to achieve gains of 1/3 and 2/5 for inputs ranging between 1.4 and 3.6 V to generate output voltage range of 0.4 to 1.27 V and can supply peak load current of 22 mA. It uses thin‐oxide MOS capacitors for their high density and achieves 75.4% peak efficiency with an input frequency of 100 MHz and a load capacitor of 10 nF. An augmenting LDO that only regulates during sudden load transients helps the converter respond fast to these transients. The chip was implemented using a 65‐nm standard CMOS process. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png International Journal of Circuit Theory and Applications Wiley

A systematic approach to designing a wide‐current range, MOS capacitor‐based switched‐capacitor DC‐DC converter with an augmenting LDO

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Publisher
Wiley Subscription Services, Inc., A Wiley Company
Copyright
Copyright © 2018 John Wiley & Sons, Ltd.
ISSN
0098-9886
eISSN
1097-007X
D.O.I.
10.1002/cta.2433
Publisher site
See Article on Publisher Site

Abstract

Switched‐capacitor DC‐DC converters (SC DC‐DC) are analyzed for loss sources, voltage regulation integrity, start‐up latency, and ripple size, while the trade‐offs between these metrics are derived. These analyses are used to design a SC DC‐DC that achieves high efficiency in a wide load current range. Four‐way interleaving was employed to reduce the output ripple and efficiency loss due to this ripple. The design can be reconfigured to achieve gains of 1/3 and 2/5 for inputs ranging between 1.4 and 3.6 V to generate output voltage range of 0.4 to 1.27 V and can supply peak load current of 22 mA. It uses thin‐oxide MOS capacitors for their high density and achieves 75.4% peak efficiency with an input frequency of 100 MHz and a load capacitor of 10 nF. An augmenting LDO that only regulates during sudden load transients helps the converter respond fast to these transients. The chip was implemented using a 65‐nm standard CMOS process.

Journal

International Journal of Circuit Theory and ApplicationsWiley

Published: Jan 1, 2018

Keywords: ; ; ; ;

References

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