A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases... IntroductionNo precise dc models exist for fully depleted silicon‐on‐insulator (FD‐SOI) metal‐oxide‐silicon field‐effect‐transistors (MOSFETs) that are specifically designated to operate at currents and voltages that are much higher than those used in today's computers and cellular phones to operate their logic and memory modules. Operation at higher currents and voltages enables the semiconductor devices in today's cellular phones to supply and transmit 0.7–1 W of radio‐frequency (rf) output power. An accurate model of these higher currents and voltages in FD‐SOI MOSFETs is key to simulate and predict their rf output power. These devices employ longer gates (350–600 nm) so they can support higher voltages at the drain (3.3–5.0 V). They also use far less gate‐legs (or gate‐fingers) in parallel and rely, instead, on wider planar gates to deliver higher output currents. These constraints on the gate architecture arise from the fact that (i) the device rf bandwidth degrades significantly when FINFETs are used in the place of devices incorporating planar gates, and that (ii) the bandwidth also degrades when the number of gate‐legs in parallel increases. Therefore, devices that incorporate longer and wider planar gates, with fewer gate‐legs in parallel, are most suited for applications that require wide rf bandwidths and higher rf http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Physica Status Solidi (A) Applications and Materials Science Wiley

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

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Publisher
Wiley Subscription Services, Inc., A Wiley Company
Copyright
© 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
ISSN
1862-6300
eISSN
1862-6319
D.O.I.
10.1002/pssa.201700419
Publisher site
See Article on Publisher Site

Abstract

IntroductionNo precise dc models exist for fully depleted silicon‐on‐insulator (FD‐SOI) metal‐oxide‐silicon field‐effect‐transistors (MOSFETs) that are specifically designated to operate at currents and voltages that are much higher than those used in today's computers and cellular phones to operate their logic and memory modules. Operation at higher currents and voltages enables the semiconductor devices in today's cellular phones to supply and transmit 0.7–1 W of radio‐frequency (rf) output power. An accurate model of these higher currents and voltages in FD‐SOI MOSFETs is key to simulate and predict their rf output power. These devices employ longer gates (350–600 nm) so they can support higher voltages at the drain (3.3–5.0 V). They also use far less gate‐legs (or gate‐fingers) in parallel and rely, instead, on wider planar gates to deliver higher output currents. These constraints on the gate architecture arise from the fact that (i) the device rf bandwidth degrades significantly when FINFETs are used in the place of devices incorporating planar gates, and that (ii) the bandwidth also degrades when the number of gate‐legs in parallel increases. Therefore, devices that incorporate longer and wider planar gates, with fewer gate‐legs in parallel, are most suited for applications that require wide rf bandwidths and higher rf

Journal

Physica Status Solidi (A) Applications and Materials ScienceWiley

Published: Jan 1, 2018

Keywords: ; ; ; ;

References

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