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Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA)

Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA) Circuits and Systems, 2013, 4, 147-156 http://dx.doi.org/10.4236/cs.2013.42020 Published Online April 2013 (http://www.scirp.org/journal/cs) Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA) Mohammad Rafiq Beigh , Mohammad Mustafa, Firdous Ahmad Department of Electronics & Instrumentation Technology, University of Kashmir, Srinagar, India Email: [email protected] Received December 4, 2012; revised January 14, 2013; accepted January 22, 2013 Copyright © 2013 Mohammad Rafiq Beigh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. ABSTRACT Quantum-dot cellular automaton (QCA) is an emerging, promising, future generation nanoelectronic computational architecture that encodes binary information as electronic charge configuration of a cell. It is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. Fundamental unit in building of QCA circuits is a QCA cell. A QCA cell is an elementary building block which can be used to build basic gates and logic devices in QCA architectures. This paper evaluates the performance of various implementations of QCA based XOR gates and proposes various novel layouts with better performance parameters. We presented the various QCA circuit design methodology for XOR gate. These layouts show less number of crossovers and lesser cell count as compared to the conventional layouts already present in the literature. These design topologies have special functions in communica- tion based circuit applications. They are particularly useful in phase detectors in digital circuits, arithmetic operations and error detection & correction circuits. The comparison of various circuit designs is also given. The proposed designs can be effectively used to realize more complex circuits. The simulations in the present work have been carried out us- ing QCADesigner tool. Keywords: Nanoelectronics; Quantum Cellular Automata (QCA); Majority Logic; Combinational Logic; XOR Gate; QCA Designer 1. Introduction approaching to its physical limits [2-4]. Any physical phenomenon that has two separate states can be used to Quantum-dot cellular automata (QCA) is an emerging express a logic variable in two valid logic states such as nanoelectronic technology that offers a revolutionary electronic spin. Quantum effect is preferred to utilize in approach to computing at nano level [1]. A very exten- representing logic rather than any other method. Quan- sive research and development in the field device tech- tum logic devices are presented under this consideration nology for the past several decades made it possible for and one of these is known as Quantum-dot Cellular Au- designers and processing engineers rapidly and consis- tomata [5,6]. QCA is an emerging paradigm which al- tently reduce semiconductor device size and operating lows operating frequencies in the range of THz and de- current. But the incessant development in device fabrica- vice integration densities about 900 times than the cur- tion on the nanometer scale is limited not only by process rent end of CMOS scaling limits. It has been predicted as technology, but also by fundamental problems arising one of the future nanotechnologies in Semiconductor from scaling, such as quantum-mechanical effects and Industries Association’s International Technology Road- severe power dissipation. In MOS devices the gate tun- map for Semiconductors (ITRS) [7]. QCA based circuits neling current increases with the future size going down have an advantage of high speed, high integrity and low to deep submicron device geometry process. As a result power consumption [8,9]. Also QCA circuits have an ad- the device and circuit characteristics drastically are devi- vantage of high parallel processing [10,11]. Recent work ated from the designer’s expectations of making it better showed that QCA can achieve high density, fast switch- suited from application point of view. Further, in several ing speed, and room temperature operation [12,13]. In re- studies it is predicted that these device technologies are cent years various QCA based combinational circuit de- Corresponding author. signs have been proposed [14-19] but comparatively less Copyright © 2013 SciRes. CS 148 M. R. BEIGH ET AL. study efforts have been made with its application in the field of communication. We present here different lay- outs of QCA based XOR structures that can be used in design and development of specific communication cir- cuits, like parity generators & checkers, error detection & correction circuits and LFSRs. These designs are effi- cient in terms of cell count, complexity and latency as compared to the already proposed designs. These designs follow the conventional design approach but due to the technology differences, they are modified for the best performance in QCA. In this paper we propose the seven novel implementa- tions of the QCA based XOR gate and presented the simulation results of these individual designs. A detail Figure 1. QCA cell and polarizations of QCA cell. comparison with regard to various characteristics of these cell. The interaction between the QCA cells is nonlinear designs is also presented. The paper has been organized that is with a small perturbation from a neighboring cell in five sections. The first and second section provides the clicks it into essentially aligned configuration either with necessary introduction and review of QCA fundamentals. P = +1 or P = −1 as will be the appropriate. The third section presents the conventional XOR imple- mentations. The various novel QCA XOR topologies 2.2. QCA Wires have been presented in the fourth section. The advan- tages of the proposed structures have been summed up as In a QCA wire, the binary signal propagates from input conclusion in the fifth section. to output because of the electrostatic interactions be- tween cells. The propagation in a 90˚ QCA wire is shown 2. QCA Fundamentals in Figure 2(a). Other than the 90˚ QCA wire, a 45˚ QCA wire can also be used as shown Figure 2(b). In this case, In this section, we briefly describe the preliminaries of the propagation of the binary signal alternates between QCA and computation mechanism using QCA cells. the two polarizations [5]. 2.1. Basic QCA Cell 2.3. QCA Majority Gate and Inverter A QCA cell is a structure comprised of four quantum- The fundamental QCA logical circuit is the three-input dots arranged in a square pattern as shown in Figure 1. majority gate that appears in Figure 3 [5]. The majority These quantum-dots are sites in which electrons are able gate produces an output that reflects the majority of the to tunnel between them but cannot leave the cell. in A puts. QCA information processing is based on the Columbic The QCA majority gate has four terminal cells out of interactions between many identical QCA cells. Each which three are representing input terminals and the re- QCA cell is constructed using four electronic sites or maining one represents the output cell [5]. Assuming that dots coupled through quantum mechanical tunneling bar- the three inputs are A, B and C, the logic function of the riers. The electronic sites represent locations that a mo- majority gate is bile electron can occupy. The cells contain two mobile electrons (or holes) which repel each other as a result of M AB,,C AB BC CA   their mutual Columbic interaction, and, in the ground The two different structures of QCA inverter is shown state, tend to occupy the diagonal sites of the cell. There- in Figure 4. An inverter is usually formed by placing the fore the cell has two degenerate ground states. These lead cells with only their corners touching. The electrostatic to two polarizations of a QCA cell, denoted as P = +1 interaction is inverted, because the quantum dots corre- and P = −1 respectively. Binary information can be en- coded in the polarization of electrons in each QCA cell. sponding to different polarizations are misaligned be- Thus, logic 0 and logic 1 are encoded in polarization P = tween the cells [20]. The second inverter is built by neigh- −1 and P = +1 respectively. Figure 1 also shows the two boring QCA cells on the diagonal, which causes Cou- possible polarizations of a QCA cell. Binary computation lomb forces to place the two electrons in opposing wells requires interaction among bits, in these devices, among of the cell with respect to the source. the cells. When a second cell is placed near the first cell, The AND and OR logic is realized by fixing the po- the coulomb interaction between the cells removes the larization of one of the inputs of the majority gate to ei- degeneracy and determines the ground state of the first ther P = −1 (logic “0”) or P = 1 (logic “1”) as shown in Copyright © 2013 SciRes. CS M. R. BEIGH ET AL. 149 (a) (b) Figure 5. QCA layout of AND, OR gate. Figure 2. (a) QCA wire (90˚); (b) QCA wire (45˚). Figure 6. QCA layout of NAND gate. (a) (b) Figure 3. (a) QCA majority gate; (b) Schematic majority gate representation. (a) (b) (a) (b) Figure 4. QCA inverters. Figure 7. The four phases of the QCA clock. Figure 5. This clocking method makes the design of QCA different The NAND function is realized by connecting AND from CMOS circuits. gate (MG) followed by an inverter. By using this 2 cell Each signal is phase shifted by 90˚ degrees. When the inverter, the area required and complexity can be mini- clock signal is low the cells are latched. When the clock mized. The layout and schematic is shown in Figure 6. signal is high the cells are relaxed and have no polariza- tion. In between the cells are either latching or relaxing 2.4. QCA Clocking when the clock is decreasing/increasing respectively. The QCA circuits require a clock, not only to synchronize 3. QCA Exclusive-OR Implementations and control information flow but also to provide the power to run the circuit since there is no external source In addition to AND, OR, NOT, NAND and NOR gates, for powering cells. The clocking of QCA can be accom- exclusive-OR (XOR) and exclusive-NOR (XNOR) gates plished by controlling the potential barriers between ad- are also used in the design of digital circuits. These have jacent quantum-dots [21,22]. With the use of four phase special functions and applications. These gates are par- clocking scheme in controlling cells, QCA processes and ticularly useful in arithmetic operations as well as error- forwards information within cells in an arranged timing detection and correction circuits. XOR and XNOR gates scheme. Cells can be grouped into zones so that the field are usually found as 2-input gates. No multiple-input influencing all the cells in the zones will be the same. XOR/XNOR gates are available since they are complex Figure 7(a) shows the four phases of QCA clock. Figure to fabricate with hardware. 7(b) shows the four available clock signals. Each signal is The exclusive-OR (XOR) performs the following logic phase shifted by 90˚ degrees. In the Switch phase, the tun- operation: neling barriers in a zone are raised. While this occurs, the ABA B AB electrons within the cell can be influenced by the Colum- bic charges of neighboring zones. Zones in the Hold The conventional schematic representation of XOR phase have a high tunneling barrier and will not change and two different QCA implementations for this layout is state, but influence other adjacent zones. Lastly, the Re- shown in Figure 8. lease and Relax decrease the tunneling barrier so that the The QCA implementation for the layout shown in Fig- zone will not influence other zones. These zones can be of ure 8(a) has been proposed by different authors [5,23]. irregular shape, but their size must be within certain limits This design needs either coplanar crossovers or multiple imposed by fabrication and dissipation concerns. Proper layers to implement. The design provided as a sample placement of these zones is critical to design efficiency. file with QCA Designer Version 2.0.3 [24] needs cross- Copyright © 2013 SciRes. CS 150 M. R. BEIGH ET AL. gate directly using AND, OR and NOT gates. However, this approach requires five gates of three different kinds. Logically, the exclusive OR (XOR) operation can also be implemented by the gate arrangements to follow. For in- stance they can also be implemented using NAND or NOR gates only. (a) 4.1. The First Design Every Boolean function can be build from (binary) Fred kin Gates (FGs), such that it has two inputs A, B and one output Y. The first design is based on Equation (1) which can be simplified as  YAB A AB B     YAB A AB B   (1)    YA  A ABABBB  YABAB The proposed QCA XOR gate has no crossovers and has cell count of 34 cells and an area of approximately 0.06 um which is less as compared to conventional lay- (b) outs. The proposed layout of this design and simulation results are shown in Figures 9 (b) and (c). 4.2. The Second Design The second design is based on Equation (2) which can be reduced to basic XOR equation as shown below. YAB AB    YABAB YA A B B A B (2)      YA A AB BABB  YA BAB (c) The proposed QCA XOR gate will require one cross- Figure 8. Conventional QCA-XOR schematic & implementa- over in order to input “A” separately out of the gate. It tion. has cell complexity of 54 cells and an area of approxi- mately 0.07 um . The proposed QCA layout of this XOR overs and uses three layers to implement. This design is gate and simulation results are shown in Figures 10(b) shown in Figure 8(b). We have proposed in this work and (c). seven different QCA based designs of XOR. These lay- outs have been designed to provide the more efficient 4.3. The Third Design configurations in terms of cell count, latency and com- plexity. The third design is based on Equation (3) which can be simplified as 4. Proposed XOR Structures  YA B AB  Exclusive OR, also known as Exclusive disjunction and symbolized by XOR, is a logical operation on two oper-  YA   B AB      (3) ands that results in a logical value of true if and only if one of the operands, but not both, has a value of true.     YABA B   This forms a fundamental logic gate in many operations.  YA BAB An XOR gate can be trivially constructed from an XNOR gate followed by a NOT gate. We can construct an XOR The QCA layout and simulation results of this design Copyright © 2013 SciRes. CS M. R. BEIGH ET AL. 151 (a) (b) (c) Figure 9. First proposed QCA XOR gate and simulation results. (a) (b) (c) Figure 10. 2nd proposed QCA XOR gate and simulation results. Copyright © 2013 SciRes. CS 152 M. R. BEIGH ET AL. are shown in Figures 11(b) and (c) respectively. The 4.6. The Sixth Design proposed QCA XOR gate does not require any crossover. The sixth design is based on the gate arrangement shown It has cell complexity of 52 cells and an area of approxi- in Figure 14(a). mately 0.08 um . It has a latency of two clock cycles. The QCA layout and simulation results of this design are shown in Figures 14(b) and (c) respectively. This de- 4.4. The Fourth Design sign has a latency of 1 clock cycle and an area of 0.07 The fourth design is based on Equation (4) which can be um . It has a cell count of 54 cells. simplified as 4.7. The Seventh Design YA AB B AB   The seventh design is based on the gate arrangement YA  A AB AB BB (4)  shown in Figure 15(a).  YAB AB The proposed QCA design has a latency of 12 de- The proposed QCA design has a latency of 2 clock cy- lays and an area of 0.05 and circuit complexity of 42 cles and an area of 0.09 and cell count of 52 cells. It does cells. The proposed QCA gate and simulation results are not require any crossover. The proposed QCA gate and shown in Figures 15(b) and (c) respectively. its simulation results are also shown in Figure 12. 5. Conclusions 4.5. The Fifth Design In this paper we have proposed efficient structures of The fifth design is based on the gate arrangement shown Quantum-dot Cellular Automata based XOR gates with in Figure 13(a). It will require one crossover in order to reduced number of QCA cells and area compared to pre- output “out” separately out of the gate. vious designs. The proposed designs have been tested The proposed QCA design has a latency of 12 clock and simulated using Bistable Approximation simulation cycles and an area of 0.06 and has a cell count of 48 cells. engine of QCA Designer version 2.0.3. The function of The QCA layout of this gate and its simulation results are the Exclusive OR gate has been verified according to the also shown in Figure 13. truth table. These structures were designed with mini- (a) (b) (c) Figure 11. 3rd proposed QCA XOR gate and simulation results. Copyright © 2013 SciRes. CS M. R. BEIGH ET AL. 153 (a) (b) (c) Figure 12. 4th proposed QCA XOR gate and simulation results. (a) (b) (c) Figure 13. 5th proposed QCA XOR gate and simulation results. Copyright © 2013 SciRes. CS 154 M. R. BEIGH ET AL. (a) (b) (c) Figure 14. 6th proposed QCA XOR gate and simulation results. (a) (b) (c) Figure 15. 7th proposed QCA XOR gate and simulation results. Copyright © 2013 SciRes. CS M. R. BEIGH ET AL. 155 Table 1. Comparison of logical structures. EXOR Logic Structures Complexity (Cell Count) Area (um ) Latency (Clocking Cycles) Figure 8(b) 84 0.08 1 Conventional Structures Figure 8(c) 64 0.07 1 First Design 34 0.06 1 (Figure 9) Second Design 54 0.07 1 (Figure 10) Third Design 52 0.08 2 (Figure 11) Fourth Design 52 0.09 2 (Figure 12) Proposed Fifth Design Structures 48 0.06 1/2 (Figure 13) Sixth Design 54 0.07 1 (Figure 14) Seventh Design 42 0.05 1/2 (Figure 15) (ITRS), 2004. mum number of cells by using cell minimization tech- http://www.itrs.net/Links/2004Update/2004Update.htm niques. The area and complexity are the major issues in [8] C. G. Smith, “Computation without Current,” Science, QCA circuit design. The proposed technique can be used Vol. 284, No. 5412, 1999, pp. 274-274. to minimize area and complexity. doi:10.1126/science.284.5412.274 Table 1 gives the comparison of proposed designs [9] J. Timler and C. S. Lent, “Power Gain and Dissipation in with that of conventional designs as shown in Figure 8. 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Budiman, plementations for Quantum Dot Cellular Automata,” Pro- “QCA Designer—A Rapid Design and Simulation Tool ceedings of the 4th IEEE Conference of Nanotechnology, for Quantum Dot Cellular Automata,” IEEE Transactions Munich, 17-19 August 2004, pp. 625-627. on Nanotechnology, Vol. 3, No. 1, 2004, pp. 26-31. doi:10.1109/TNANO.2003.820815 [21] G. Snider, A. Orlov, C. S. Lent, G. Bernstein, M. Lie- Copyright © 2013 SciRes. CS http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Circuits and Systems Unpaywall

Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA)

Beigh, Mohammad Rafiq; Mustafa, Mohammad; Ahmad, Firdous
Circuits and Systems – Jan 1, 2013
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Circuits and Systems, 2013, 4, 147-156 http://dx.doi.org/10.4236/cs.2013.42020 Published Online April 2013 (http://www.scirp.org/journal/cs) Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA) Mohammad Rafiq Beigh , Mohammad Mustafa, Firdous Ahmad Department of Electronics & Instrumentation Technology, University of Kashmir, Srinagar, India Email: [email protected] Received December 4, 2012; revised January 14, 2013; accepted January 22, 2013 Copyright © 2013 Mohammad Rafiq Beigh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. ABSTRACT Quantum-dot cellular automaton (QCA) is an emerging, promising, future generation nanoelectronic computational architecture that encodes binary information as electronic charge configuration of a cell. It is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. Fundamental unit in building of QCA circuits is a QCA cell. A QCA cell is an elementary building block which can be used to build basic gates and logic devices in QCA architectures. This paper evaluates the performance of various implementations of QCA based XOR gates and proposes various novel layouts with better performance parameters. We presented the various QCA circuit design methodology for XOR gate. These layouts show less number of crossovers and lesser cell count as compared to the conventional layouts already present in the literature. These design topologies have special functions in communica- tion based circuit applications. They are particularly useful in phase detectors in digital circuits, arithmetic operations and error detection & correction circuits. The comparison of various circuit designs is also given. The proposed designs can be effectively used to realize more complex circuits. The simulations in the present work have been carried out us- ing QCADesigner tool. Keywords: Nanoelectronics; Quantum Cellular Automata (QCA); Majority Logic; Combinational Logic; XOR Gate; QCA Designer 1. Introduction approaching to its physical limits [2-4]. Any physical phenomenon that has two separate states can be used to Quantum-dot cellular automata (QCA) is an emerging express a logic variable in two valid logic states such as nanoelectronic technology that offers a revolutionary electronic spin. Quantum effect is preferred to utilize in approach to computing at nano level [1]. A very exten- representing logic rather than any other method. Quan- sive research and development in the field device tech- tum logic devices are presented under this consideration nology for the past several decades made it possible for and one of these is known as Quantum-dot Cellular Au- designers and processing engineers rapidly and consis- tomata [5,6]. QCA is an emerging paradigm which al- tently reduce semiconductor device size and operating lows operating frequencies in the range of THz and de- current. But the incessant development in device fabrica- vice integration densities about 900 times than the cur- tion on the nanometer scale is limited not only by process rent end of CMOS scaling limits. It has been predicted as technology, but also by fundamental problems arising one of the future nanotechnologies in Semiconductor from scaling, such as quantum-mechanical effects and Industries Association’s International Technology Road- severe power dissipation. In MOS devices the gate tun- map for Semiconductors (ITRS) [7]. QCA based circuits neling current increases with the future size going down have an advantage of high speed, high integrity and low to deep submicron device geometry process. As a result power consumption [8,9]. Also QCA circuits have an ad- the device and circuit characteristics drastically are devi- vantage of high parallel processing [10,11]. Recent work ated from the designer’s expectations of making it better showed that QCA can achieve high density, fast switch- suited from application point of view. Further, in several ing speed, and room temperature operation [12,13]. In re- studies it is predicted that these device technologies are cent years various QCA based combinational circuit de- Corresponding author. signs have been proposed [14-19] but comparatively less Copyright © 2013 SciRes. CS 148 M. R. BEIGH ET AL. study efforts have been made with its application in the field of communication. We present here different lay- outs of QCA based XOR structures that can be used in design and development of specific communication cir- cuits, like parity generators & checkers, error detection & correction circuits and LFSRs. These designs are effi- cient in terms of cell count, complexity and latency as compared to the already proposed designs. These designs follow the conventional design approach but due to the technology differences, they are modified for the best performance in QCA. In this paper we propose the seven novel implementa- tions of the QCA based XOR gate and presented the simulation results of these individual designs. A detail Figure 1. QCA cell and polarizations of QCA cell. comparison with regard to various characteristics of these cell. The interaction between the QCA cells is nonlinear designs is also presented. The paper has been organized that is with a small perturbation from a neighboring cell in five sections. The first and second section provides the clicks it into essentially aligned configuration either with necessary introduction and review of QCA fundamentals. P = +1 or P = −1 as will be the appropriate. The third section presents the conventional XOR imple- mentations. The various novel QCA XOR topologies 2.2. QCA Wires have been presented in the fourth section. The advan- tages of the proposed structures have been summed up as In a QCA wire, the binary signal propagates from input conclusion in the fifth section. to output because of the electrostatic interactions be- tween cells. The propagation in a 90˚ QCA wire is shown 2. QCA Fundamentals in Figure 2(a). Other than the 90˚ QCA wire, a 45˚ QCA wire can also be used as shown Figure 2(b). In this case, In this section, we briefly describe the preliminaries of the propagation of the binary signal alternates between QCA and computation mechanism using QCA cells. the two polarizations [5]. 2.1. Basic QCA Cell 2.3. QCA Majority Gate and Inverter A QCA cell is a structure comprised of four quantum- The fundamental QCA logical circuit is the three-input dots arranged in a square pattern as shown in Figure 1. majority gate that appears in Figure 3 [5]. The majority These quantum-dots are sites in which electrons are able gate produces an output that reflects the majority of the to tunnel between them but cannot leave the cell. in A puts. QCA information processing is based on the Columbic The QCA majority gate has four terminal cells out of interactions between many identical QCA cells. Each which three are representing input terminals and the re- QCA cell is constructed using four electronic sites or maining one represents the output cell [5]. Assuming that dots coupled through quantum mechanical tunneling bar- the three inputs are A, B and C, the logic function of the riers. The electronic sites represent locations that a mo- majority gate is bile electron can occupy. The cells contain two mobile electrons (or holes) which repel each other as a result of M AB,,C AB BC CA   their mutual Columbic interaction, and, in the ground The two different structures of QCA inverter is shown state, tend to occupy the diagonal sites of the cell. There- in Figure 4. An inverter is usually formed by placing the fore the cell has two degenerate ground states. These lead cells with only their corners touching. The electrostatic to two polarizations of a QCA cell, denoted as P = +1 interaction is inverted, because the quantum dots corre- and P = −1 respectively. Binary information can be en- coded in the polarization of electrons in each QCA cell. sponding to different polarizations are misaligned be- Thus, logic 0 and logic 1 are encoded in polarization P = tween the cells [20]. The second inverter is built by neigh- −1 and P = +1 respectively. Figure 1 also shows the two boring QCA cells on the diagonal, which causes Cou- possible polarizations of a QCA cell. Binary computation lomb forces to place the two electrons in opposing wells requires interaction among bits, in these devices, among of the cell with respect to the source. the cells. When a second cell is placed near the first cell, The AND and OR logic is realized by fixing the po- the coulomb interaction between the cells removes the larization of one of the inputs of the majority gate to ei- degeneracy and determines the ground state of the first ther P = −1 (logic “0”) or P = 1 (logic “1”) as shown in Copyright © 2013 SciRes. CS M. R. BEIGH ET AL. 149 (a) (b) Figure 5. QCA layout of AND, OR gate. Figure 2. (a) QCA wire (90˚); (b) QCA wire (45˚). Figure 6. QCA layout of NAND gate. (a) (b) Figure 3. (a) QCA majority gate; (b) Schematic majority gate representation. (a) (b) (a) (b) Figure 4. QCA inverters. Figure 7. The four phases of the QCA clock. Figure 5. This clocking method makes the design of QCA different The NAND function is realized by connecting AND from CMOS circuits. gate (MG) followed by an inverter. By using this 2 cell Each signal is phase shifted by 90˚ degrees. When the inverter, the area required and complexity can be mini- clock signal is low the cells are latched. When the clock mized. The layout and schematic is shown in Figure 6. signal is high the cells are relaxed and have no polariza- tion. In between the cells are either latching or relaxing 2.4. QCA Clocking when the clock is decreasing/increasing respectively. The QCA circuits require a clock, not only to synchronize 3. QCA Exclusive-OR Implementations and control information flow but also to provide the power to run the circuit since there is no external source In addition to AND, OR, NOT, NAND and NOR gates, for powering cells. The clocking of QCA can be accom- exclusive-OR (XOR) and exclusive-NOR (XNOR) gates plished by controlling the potential barriers between ad- are also used in the design of digital circuits. These have jacent quantum-dots [21,22]. With the use of four phase special functions and applications. These gates are par- clocking scheme in controlling cells, QCA processes and ticularly useful in arithmetic operations as well as error- forwards information within cells in an arranged timing detection and correction circuits. XOR and XNOR gates scheme. Cells can be grouped into zones so that the field are usually found as 2-input gates. No multiple-input influencing all the cells in the zones will be the same. XOR/XNOR gates are available since they are complex Figure 7(a) shows the four phases of QCA clock. Figure to fabricate with hardware. 7(b) shows the four available clock signals. Each signal is The exclusive-OR (XOR) performs the following logic phase shifted by 90˚ degrees. In the Switch phase, the tun- operation: neling barriers in a zone are raised. While this occurs, the ABA B AB electrons within the cell can be influenced by the Colum- bic charges of neighboring zones. Zones in the Hold The conventional schematic representation of XOR phase have a high tunneling barrier and will not change and two different QCA implementations for this layout is state, but influence other adjacent zones. Lastly, the Re- shown in Figure 8. lease and Relax decrease the tunneling barrier so that the The QCA implementation for the layout shown in Fig- zone will not influence other zones. These zones can be of ure 8(a) has been proposed by different authors [5,23]. irregular shape, but their size must be within certain limits This design needs either coplanar crossovers or multiple imposed by fabrication and dissipation concerns. Proper layers to implement. The design provided as a sample placement of these zones is critical to design efficiency. file with QCA Designer Version 2.0.3 [24] needs cross- Copyright © 2013 SciRes. CS 150 M. R. BEIGH ET AL. gate directly using AND, OR and NOT gates. However, this approach requires five gates of three different kinds. Logically, the exclusive OR (XOR) operation can also be implemented by the gate arrangements to follow. For in- stance they can also be implemented using NAND or NOR gates only. (a) 4.1. The First Design Every Boolean function can be build from (binary) Fred kin Gates (FGs), such that it has two inputs A, B and one output Y. The first design is based on Equation (1) which can be simplified as  YAB A AB B     YAB A AB B   (1)    YA  A ABABBB  YABAB The proposed QCA XOR gate has no crossovers and has cell count of 34 cells and an area of approximately 0.06 um which is less as compared to conventional lay- (b) outs. The proposed layout of this design and simulation results are shown in Figures 9 (b) and (c). 4.2. The Second Design The second design is based on Equation (2) which can be reduced to basic XOR equation as shown below. YAB AB    YABAB YA A B B A B (2)      YA A AB BABB  YA BAB (c) The proposed QCA XOR gate will require one cross- Figure 8. Conventional QCA-XOR schematic & implementa- over in order to input “A” separately out of the gate. It tion. has cell complexity of 54 cells and an area of approxi- mately 0.07 um . The proposed QCA layout of this XOR overs and uses three layers to implement. This design is gate and simulation results are shown in Figures 10(b) shown in Figure 8(b). We have proposed in this work and (c). seven different QCA based designs of XOR. These lay- outs have been designed to provide the more efficient 4.3. The Third Design configurations in terms of cell count, latency and com- plexity. The third design is based on Equation (3) which can be simplified as 4. Proposed XOR Structures  YA B AB  Exclusive OR, also known as Exclusive disjunction and symbolized by XOR, is a logical operation on two oper-  YA   B AB      (3) ands that results in a logical value of true if and only if one of the operands, but not both, has a value of true.     YABA B   This forms a fundamental logic gate in many operations.  YA BAB An XOR gate can be trivially constructed from an XNOR gate followed by a NOT gate. We can construct an XOR The QCA layout and simulation results of this design Copyright © 2013 SciRes. CS M. R. BEIGH ET AL. 151 (a) (b) (c) Figure 9. First proposed QCA XOR gate and simulation results. (a) (b) (c) Figure 10. 2nd proposed QCA XOR gate and simulation results. Copyright © 2013 SciRes. CS 152 M. R. BEIGH ET AL. are shown in Figures 11(b) and (c) respectively. The 4.6. The Sixth Design proposed QCA XOR gate does not require any crossover. The sixth design is based on the gate arrangement shown It has cell complexity of 52 cells and an area of approxi- in Figure 14(a). mately 0.08 um . It has a latency of two clock cycles. The QCA layout and simulation results of this design are shown in Figures 14(b) and (c) respectively. This de- 4.4. The Fourth Design sign has a latency of 1 clock cycle and an area of 0.07 The fourth design is based on Equation (4) which can be um . It has a cell count of 54 cells. simplified as 4.7. The Seventh Design YA AB B AB   The seventh design is based on the gate arrangement YA  A AB AB BB (4)  shown in Figure 15(a).  YAB AB The proposed QCA design has a latency of 12 de- The proposed QCA design has a latency of 2 clock cy- lays and an area of 0.05 and circuit complexity of 42 cles and an area of 0.09 and cell count of 52 cells. It does cells. The proposed QCA gate and simulation results are not require any crossover. The proposed QCA gate and shown in Figures 15(b) and (c) respectively. its simulation results are also shown in Figure 12. 5. Conclusions 4.5. The Fifth Design In this paper we have proposed efficient structures of The fifth design is based on the gate arrangement shown Quantum-dot Cellular Automata based XOR gates with in Figure 13(a). It will require one crossover in order to reduced number of QCA cells and area compared to pre- output “out” separately out of the gate. vious designs. The proposed designs have been tested The proposed QCA design has a latency of 12 clock and simulated using Bistable Approximation simulation cycles and an area of 0.06 and has a cell count of 48 cells. engine of QCA Designer version 2.0.3. The function of The QCA layout of this gate and its simulation results are the Exclusive OR gate has been verified according to the also shown in Figure 13. truth table. These structures were designed with mini- (a) (b) (c) Figure 11. 3rd proposed QCA XOR gate and simulation results. Copyright © 2013 SciRes. CS M. R. BEIGH ET AL. 153 (a) (b) (c) Figure 12. 4th proposed QCA XOR gate and simulation results. (a) (b) (c) Figure 13. 5th proposed QCA XOR gate and simulation results. Copyright © 2013 SciRes. CS 154 M. R. BEIGH ET AL. (a) (b) (c) Figure 14. 6th proposed QCA XOR gate and simulation results. (a) (b) (c) Figure 15. 7th proposed QCA XOR gate and simulation results. Copyright © 2013 SciRes. CS M. R. BEIGH ET AL. 155 Table 1. Comparison of logical structures. EXOR Logic Structures Complexity (Cell Count) Area (um ) Latency (Clocking Cycles) Figure 8(b) 84 0.08 1 Conventional Structures Figure 8(c) 64 0.07 1 First Design 34 0.06 1 (Figure 9) Second Design 54 0.07 1 (Figure 10) Third Design 52 0.08 2 (Figure 11) Fourth Design 52 0.09 2 (Figure 12) Proposed Fifth Design Structures 48 0.06 1/2 (Figure 13) Sixth Design 54 0.07 1 (Figure 14) Seventh Design 42 0.05 1/2 (Figure 15) (ITRS), 2004. mum number of cells by using cell minimization tech- http://www.itrs.net/Links/2004Update/2004Update.htm niques. The area and complexity are the major issues in [8] C. G. Smith, “Computation without Current,” Science, QCA circuit design. The proposed technique can be used Vol. 284, No. 5412, 1999, pp. 274-274. to minimize area and complexity. doi:10.1126/science.284.5412.274 Table 1 gives the comparison of proposed designs [9] J. Timler and C. S. Lent, “Power Gain and Dissipation in with that of conventional designs as shown in Figure 8. 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