Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE—STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32–3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55–4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

Loading next page...
 
/lp/springer_journal/upset-resilient-ram-on-stg-dice-memory-elements-with-the-spaced-Icgot0WdaT
Publisher
Pleiades Publishing
Copyright
Copyright © 2016 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739716050085
Publisher site
See Article on Publisher Site

Abstract

The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE—STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32–3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55–4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells.

Journal

Russian MicroelectronicsSpringer Journals

Published: Feb 9, 2017

References

You’re reading a free preview. Subscribe to read the entire article.


DeepDyve is your
personal research library

It’s your single place to instantly
discover and read the research
that matters to you.

Enjoy affordable access to
over 12 million articles from more than
10,000 peer-reviewed journals.

All for just $49/month

Explore the DeepDyve Library

Unlimited reading

Read as many articles as you need. Full articles with original layout, charts and figures. Read online, from anywhere.

Stay up to date

Keep up with your field with Personalized Recommendations and Follow Journals to get automatic updates.

Organize your research

It’s easy to organize your research with our built-in tools.

Your journals are on DeepDyve

Read from thousands of the leading scholarly journals from SpringerNature, Elsevier, Wiley-Blackwell, Oxford University Press and more.

All the latest content is available, no embargo periods.

See the journals in your area

DeepDyve Freelancer

DeepDyve Pro

Price
FREE
$49/month

$360/year
Save searches from
Google Scholar,
PubMed
Create lists to
organize your research
Export lists, citations
Read DeepDyve articles
Abstract access only
Unlimited access to over
18 million full-text articles
Print
20 pages/month
PDF Discount
20% off