Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE—STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32–3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55–4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells. Russian Microelectronics Springer Journals

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

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Pleiades Publishing
Copyright © 2016 by Pleiades Publishing, Ltd.
Engineering; Electrical Engineering
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