Ultra-low power incremental delta-sigma ADC for energy harvesting sensor applications

Ultra-low power incremental delta-sigma ADC for energy harvesting sensor applications This paper presents an ultra-low power incremental $${\varDelta {\Sigma }}$$ Δ Σ ADC with flexible sampling frequency, accuracy, and operational duty-cycle. The flexibility and low leakage power enable efficient scaling of average power together with performance. This allows simultaneous optimization of the sensor system (1) for various multiplexed, both on-chip and off-chip sensor interfaces, and (2) for a wide range of available harvested energy. The architecture allows further flexibility as it can be used in regular continuous $${\varDelta {\Sigma }}$$ Δ Σ mode as well, without trading off accuracy. The ADC was implemented in a 180 nm CMOS process, on the same ASIC with a temperature sensor, pressure sensor and energy harvesting functionalities. The ADC has a nominal power consumption of $$1.3\,\upmu$$ 1.3 μ W, SNDR of 68 dB and BW of 200 Hz, denoting a $$FOM_w =1.58$$ F O M w = 1.58  pJ/conv. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Analog Integrated Circuits and Signal Processing Springer Journals

Ultra-low power incremental delta-sigma ADC for energy harvesting sensor applications

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Publisher
Springer US
Copyright
Copyright © 2017 by Springer Science+Business Media, LLC
Subject
Engineering; Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing
ISSN
0925-1030
eISSN
1573-1979
D.O.I.
10.1007/s10470-017-0999-y
Publisher site
See Article on Publisher Site

Abstract

This paper presents an ultra-low power incremental $${\varDelta {\Sigma }}$$ Δ Σ ADC with flexible sampling frequency, accuracy, and operational duty-cycle. The flexibility and low leakage power enable efficient scaling of average power together with performance. This allows simultaneous optimization of the sensor system (1) for various multiplexed, both on-chip and off-chip sensor interfaces, and (2) for a wide range of available harvested energy. The architecture allows further flexibility as it can be used in regular continuous $${\varDelta {\Sigma }}$$ Δ Σ mode as well, without trading off accuracy. The ADC was implemented in a 180 nm CMOS process, on the same ASIC with a temperature sensor, pressure sensor and energy harvesting functionalities. The ADC has a nominal power consumption of $$1.3\,\upmu$$ 1.3 μ W, SNDR of 68 dB and BW of 200 Hz, denoting a $$FOM_w =1.58$$ F O M w = 1.58  pJ/conv.

Journal

Analog Integrated Circuits and Signal ProcessingSpringer Journals

Published: Jun 29, 2017

References

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