Challenges and experimental results concerning the filling of feature-to-feature gaps on the stepped surface of a ULSI chip are reviewed. The filler is an SiO2-based insulator in the form of a CVD thin film. A conceptual framework for evaluating the gap-fill capabilities of CVD processes is defined. It essentially characterizes a process in terms of step coverage and the parameter k = H/G 2, where H is the gap depth and G is the minimum width of a gap that can be filled void-free by the process. This strategy is extended to the case where deposition is followed by planarization, as with glasses. The approach proposed enables one to predict the performance of practical processes and to significantly reduce the amount of experimental work required.
Russian Microelectronics – Springer Journals
Published: Oct 13, 2004
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