ISSN 1063-7397, Russian Microelectronics, 2006, Vol. 35, No. 5, pp. 337–344. © Pleiades Publishing, Inc., 2006.
Original Russian Text © M.I. Gorlov, A.V. Strogonov, D.Yu. Smirnov, 2006, published in Mikroelektronika, 2006, Vol. 35, No. 5, pp. 392–400.
337
INTRODUCTION
There is wide agreement that electrostatic discharge
(ESD) can lead to degradation as well as catastrophic
failures of semiconductor devices. In practice, however,
it is difficult to discriminate between ESD-induced deg-
radation failures and ones caused by overloading [1].
In silicon bipolar junction transistors, ESD acceler-
ates the degradation of the current gain factor
β
, which
follows a pattern similar to that caused by thermal
stress or ionizing irradiation.
In this study, the Box–Jenkins procedure is
employed to investigate the ESD-induced degradation
of low-power discrete silicon bipolar transistors
(KT361E2). It is considered one of the most effective
strategies for predicting the behavior of systems
described by time series, having found many uses in
production control, econometrics, time-series filtering,
aerospace engineering and navigation, and telecommuni-
cations [2]. In electronics the Box–Jenkins procedure has
achieved extensive use as a tool for the statistical simula-
tion of failure rates in electronic components; it has also
proven to be useful for describing the performance degra-
dation of high-reliability integrated circuits.
The Box–Jenkins procedure is implemented in the
statistical software packages SYSTAT 7.0, SAS,
WINKS, STATGRAPHICS, SPSS, and Statistica for
Windows; it is also included in the Mezozavr package
specifically designed for time-series analysis. In addi-
tion, the packages offer such time-series options as
smoothing, filtering, spectral analysis, seasonal adjust-
ment, and regression analysis. The SPSS Trends tool
serves to improve time-series forecasting. It allows one
to apply autoregressive integrated moving-average
(ARIMA) models to such tasks as process quality con-
trol, forecasting-system operation, sales forecasting,
and social research. In Russia, Pro-Invest Konsalting’s
Forecast Expert employs the Box–Jenkins procedure to
forecast the behavior of any economic variable from a
suitably large number of measurements made over a given
time period. The package has found application in fore-
casting of exchange rates and share prices at the Russian
Federation’s Central Bank, Sberbank, and some major
Russian private banks [3]. Returning to electronics appli-
cations, we note that autoregressive (AR) models are used
for coding audio signals in GSM and DECT networks,
which implement time-division multiple access [4]. In
code-division multiple-access networks, the Code-
Excited Linear Prediction (CELP) algorithm is adopted as
a means of digitizing audio signals with variable rate.
Sample-autocorrelation and spectral distributions
may be investigated by the generalized linear model. It
works on the premise that the discrete white noise
a
t
(a sequence of independent identically distributed nor-
mal random variables) can be converted into a process
X
t
by means of a linear filter. This suggests a way to
produce a time series from a given one, in which case
linear filtering is expressed as follows [5]:
AR models were originally introduced to describe
stochastic systems that show inertia and can be in stable
equilibrium, as in mechanics. A
p
th-order AR model,
AR(
p
), is defined by
X
t
ψ
0
a
t
ψ
1
a
t 1–
ψ
2
a
t 2–
…+++ ψ
i
a
ti–
.
0
∞
∑
==
Transistor-Degradation Prediction by Time-Series Analysis
M. I. Gorlov, A. V. Strogonov, and D. Yu. Smirnov
Voronezh State Technical University, Voronezh, Russia
e-mail: andreis@hotmail.ru
Received May 2, 2005
Abstract
—In silicon bipolar junction transistors, electrostatic discharge (ESD) is known to accelerate the deg-
radation of the current gain factor
β
, which follows a pattern similar to that caused by thermal stress or ionizing
irradiation. We use autoregressive integrated moving-average (ARIMA) models to predict the degradation of
β
from ESD- or life-test data.
PACS numbers: 85.30.De
DOI:
10.1134/S106373970605009X
CIRCUIT ANALYSIS
AND SYNTHESIS