A theoretical basis is proposed for the layout optimization of flash ADCs to be operated in the subnanosecond range. A mathematical model and a layout-synthesis procedure are presented for comparator signal lines with distributed parameters. An algorithm is described for the computer-aided construction and solution of equations for comparator transfer functions. The results are reported of a transient analysis for the comparators of microwave ADCs differing in the arrangement and parameters of the microstrip signal lines. Layouts are displayed for 6-bit ADCs with different configurations of the comparator subsystem. The results are presented of a time-domain computer simulation for 6-bit ADCs.
Russian Microelectronics – Springer Journals
Published: May 19, 2005
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