ISSN 10637397, Russian Microelectronics, 2012, Vol. 41, No. 7, pp. 410–414. © Pleiades Publishing, Ltd., 2012.
Original Russian Text © G.G. Zagyladin, 2011, published in Izvestiya Vysshikh Uchebnykh Zavedenii. Elektronika, 2011, No. 4, pp. 39–44.
Increased attention to computeraided design
(CAD) of VLSIs is associated not only with a contin
uous increase in the degree of integration but also with
the fundamental complication of the requirements for
designed circuits. The conventional criteria of the
physical designing remain topical, but, at the same
time, fundamentally new criteria and rules also appear.
A decrease in topological norms to 45 nm and
lower leads to a fundamental increase in production
cost. Therefore, the problem of minimizing the chip
area becomes even more urgent. Performance of
nanometer VLSIs depends mainly on the length of
interconnections; therefore, minimizing the total
wirelength is one of the most important designing cri
teria. An increase in the amount of liberated heat leads
to the problem of its dissipation and the uniform dis
tribution over the chip area.
In connection with an increase in the influence of
deep submicron effects (crosstalk, IRdrop) on the
operability of nanometer VLSIs, it is necessary to take
them into account immediately at the stages of place
ment and routing. The optical proximity correction
(OPC) often passes via the addition of fundamentally
new design rules, which should be fulfilled during
physical designing. Additional requirements on the
maximal and minimal layout density are also intro
duced, which should ensure the quality of the chemi
Some problems under consideration require apply
ing the complex approach, while others can be
resolved at the routing stage. The routing problem,
because of its computational complexity, is divided
into global  and detailed. When performing the glo
bal routing, the draft interconnecton layout is formed.
Then, the final solution is sought in a form of the set of
traces at the stage of detailed routing.
The main tasks of global routing are the reduction
of the total wirelength, satisfying the timing con
straints, and provision of 100% routability. The reduc
tion of the wirelength affects the magnitude of delays
and consumed power, and the appearance of a cross
talk is also possible. The local density of the intercon
nections does not only affect the circuit routability but
also touches the distribution of the liberated heat on
conductors and the possibility to eliminate the cross
talk and electromigration.
Conventionally, the solution is sought in two stages.
At the first stage, the initial solution is designed, and at
the second stage, it is optimized. During the construc
tion of the initial solution, all circuits are classified
into twoterminal circuits, for which the algorithms of
the monotonic and pattern routing are used , and
multiterminal circuits, for which FLUTE is used .
As a rule, the second stage is reduced to dividing and
rerouting separate interconnections, for which the
algorithms of the labyrinth (
*—search ), pattern,
and monotonic routing are used. The quality of the
acquired solutions depends on the structure of Steiner
trees very strongly.
THE DESCRIPTION OF THE APPROACH
The core of the suggested approach  lies in the arti
ficial limitation of the optimization quality by one of the
criteria in order to extend the optimization possibilities
by other criteria. Not one but a multitude (family) of
solutions is constructed for each net, and Steiner mini
mal tree (SMT) families with various topologies are used.
This allows us to take into account several criteria imme
diately during the synthesis of the solution rather than to
To ensure the flexibility of the suggested approach,
this work is performed in several stages (Fig. 1), each of
which operates with the Steiner tree family.
To acquire the SMT family, a set of spanning trees
are formed, and the deviation of the cost of each tree
from the minimal cost does not exceed the value of the
. With the subsequent optimi
The Method for Global Routing of Submicron VLSIs Based
on the Use of the Family of the Steiner Trees
G. G. Zaglyadin
Moscow Institute of Electronic Engineering (Technical University), proezd 4806, 5, Zelenograd, Moscow, 124498 Russia
Received December 24, 2010
—The method for the solution of the problem of global routing of signal VLSI circuits based on the
use of the family of Steiner trees for each circuit is described. The method makes it possible to minimize both
the circuit length and the local routing density. The results of the investigation of this method are presented.