Implementations of the basic ternary logic element and digital units with the use of the balanced three-valued code are suggested. The logic states are supported by a bipolar power source. The circuits considered in the study are expected to be produced by the standard MOS technology. The results of simulation of и V-supplied units with the use of the parameters of the 0.18 μm MOS technology based on the platform Cadence Virtuoso are presented. The steady-state current consumption of the basic ternary logic element does not exceed 300 nA. The solutions suggested in the study provide the processing of a ternary signal with the minimum pulse duration of about 10 ns.
Russian Microelectronics – Springer Journals
Published: May 17, 2009
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