The design of ternary logic units on the basis of the standard MOS technology

The design of ternary logic units on the basis of the standard MOS technology Implementations of the basic ternary logic element and digital units with the use of the balanced three-valued code are suggested. The logic states are supported by a bipolar power source. The circuits considered in the study are expected to be produced by the standard MOS technology. The results of simulation of и V-supplied units with the use of the parameters of the 0.18 μm MOS technology based on the platform Cadence Virtuoso are presented. The steady-state current consumption of the basic ternary logic element does not exceed 300 nA. The solutions suggested in the study provide the processing of a ternary signal with the minimum pulse duration of about 10 ns. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

The design of ternary logic units on the basis of the standard MOS technology

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2009 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739709030081
Publisher site
See Article on Publisher Site

Abstract

Implementations of the basic ternary logic element and digital units with the use of the balanced three-valued code are suggested. The logic states are supported by a bipolar power source. The circuits considered in the study are expected to be produced by the standard MOS technology. The results of simulation of и V-supplied units with the use of the parameters of the 0.18 μm MOS technology based on the platform Cadence Virtuoso are presented. The steady-state current consumption of the basic ternary logic element does not exceed 300 nA. The solutions suggested in the study provide the processing of a ternary signal with the minimum pulse duration of about 10 ns.

Journal

Russian MicroelectronicsSpringer Journals

Published: May 17, 2009

References

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