ISSN 10637397, Russian Microelectronics, 2013, Vol. 42, No. 4, pp. 253–259. © Pleiades Publishing, Ltd., 2013.
Original Russian Text © D.L. Osipov, Yu.I. Bocharov, V.A. Butuzov, 2013, published in Mikroelektronika, 2013, Vol. 42, No. 4, pp. 314–320.
The approach to the topdown design of integrated
circuits using the VerilogA description languages
implies the consecutive passage from the higher
abstraction level of the system description to the lower
one. Thus, it is possible to model the system operation
and to determine the requirements to separate blocks at
early design stages [1–3]. The previous modification of
the topdown approach with the refinement of the fab
ricated samples by the results of the lowlevel modeling
or testing of the fabricated samples implies the intro
duction of the informational abstraction acquired at a
lower level [4, 5]. Thus, it becomes possible to correct
the requirements for the system based on the analysis of
the influence of the actual block characteristics on the
system, which is ideal in other aspects.
A split capacitor array involved in the successive
approximation register (SAR) analogtodigital con
verter (ADC) is a rather complex functional unit,
largely affecting the ADC characteristics in general.
The VerilogA highlevel model presented in this study
makes it possible to take into account the data acquired
during the extraction by the Mentor Graphics Calibre
of the split capacitor array topology during modeling at
a high abstraction level and, correspondingly, at a very
high rate. We present the analysis of the connection
between the digitaltoanalog converter (DAC) and
ADC characteristics in general in Section 2. The influ
ence of parasitic capacitors on the DAC characteristics
is considered in Section 3. The VerilogA model and its
application in the context of the approach to the top
down design of integrated microcircuits are considered
in Section 4.
2. INFLUENCE OF THE INTERNAL DAC
ON THE ADC CHARACTERISTICS
Figure 1 shows the block diagram of the SAR ADC.
One popular implementation of this ADC type is with
the switching capacitor DAC additionally playing the
role of the sample and hold amplifier (SHA). The DAC
circuit is shown in Fig. 2. In order to reduce the area
occupied by the ADC and the consumed current, the
split capacitor array is split into two halfarrays by
After finishing sampling, voltage
lished at the output of the split capacitor array. Further,
during the conversion, voltage
is stated at the
The Behavioral Model of a Split Capacitor Array Involved
in the Successive Approximation Register ADC
and Taking into Account the Effect of Parasitic Capacitors
D. L. Osipov, Yu. I. Bocharov, and V. A. Butuzov
National Research Nuclear University MEPHI, Kashirskoe sh. 31, Moscow, 115409 Russia
Received February 25, 2012
—The analysis of the effect of the parasitic capacitors on the split capacitor array digitalto analog
converter for use in the successive approximation register analogtodigital converter is presented. The Ver
ilogA model of the split capacitor array is developed based on the analysis. The advantages of using this
model in the context of the topdown design methodology are considered.
Block diagram of the SAR ADC. SHA is the sample
and hold amplifier, DAC is the digitaltoanalog converter,
and SAR is the successive approximation register.