ISSN 10637397, Russian Microelectronics, 2011, Vol. 40, No. 7, pp. 491–496. © Pleiades Publishing, Ltd., 2011.
Original Russian Text © V.A. Bachmanov, S.A. Bobrikov, I.V. Zabolotnov, 2009, published in Izvestiya Vysshikh Uchebnykh Zavedenii. Elektronika, 2009, No. 5, pp. 35–43.
Memory blocks of different classes are needed in
any systemonchip (SoC). They allow for the dictio
narybit parameterization of their construction.
Therefore, it is advantageous to design them automat
ically by means of socalled memory compilers.
Abroad, such compilers, targeted at sub
nologies, are already in use [1, 2]. The required
parameters of the memory unit as one of SoC blocks
are set at the input of the compiler, and after about a
minute the circuit’s topological solution and the
behavioral model of the block in CAD SoC formats,
such as Cadence and Synopsys, are obtained. Obtain
ing dynamical characteristics (temporal characteriza
tion) of any variant of memory takes
10 s [1, 2]. As
a result, the design time of the SoC at development
centers was significantly reduced, and the institutional
and financial aspects of obtaining the memory unit of
the required class and with the required parameters
became less urgent.
In the Russian Federation, similar research teams
do not have such an opportunity. As a result, the SoC
design period is unreasonably prolonged. The devel
opment of domestic memory compilers remains rele
vant. The main problem of such developments is a
characterization of compilable memory unit variants
in the temporal area, i.e., in an unacceptable combi
nation of accuracyspeed performance indicators of
all known algorithms for calculating (simulating) sig
nal delays, if this calculation is performed for each
case directly in the compiler, or if any external com
puter is initiated from it each time.
For example, using this approach, the character
ization of the memory unit variant by means of the
SPICE simulator takes ~3
. On the con
trary, the application of the same tools of logictempo
ral modeling carries an unacceptably high level of
error due to the presence of functionally important
analog modes in the memory unit concept. In the case
m design rules the situation is more compli
cated, since the temporary tables, obtained by SPICE
for logic elements, may have reduced accuracy, partic
ularly because of the short duration of signal fronts (5–
Principles of temporal characterization of com
pilable memory units.
In this paper, the specified prob
lem is solved for static RAM compilers, aimed at
m CMOS technologies. The solution is reduced
to the application of the following conceptually
1. A preliminary application of the mentioned
algorithms (programs, simulators) outside the com
piler. This condition allows us to consider the accu
racyspeed indicator for the part of the algorithms in
the field of acceptable compromises (precomputation
2. The selection of the most promising means from
point 1, followed by the identification of their condi
tions and modes of operation (principle of selection
and adjustment of algorithms).
3. The improvement of accuracyspeed indicators
of the selected algorithms due to their specialization
and/or use of additional procedures (algorithm spe
4. The computation of delays only for the selected
reference variants of memory units with subsequent
recording of the results into a database (DB) of the
compiler (principle of the use of linear parts of the
delaymemory variant dependence).
In the context of point 2, the most promising algo
rithms include the ones that allow for the multiproces
sor calculation of the circuit model.
This concept presupposes storing and executing
the interpolating auxiliary program in the compiler.
The time of its execution is
as mentioned above.
In the speedaccuracy relation, the term
(offset) has two stages; i.e., the lower level (basic)
Temporal Characterization of Static CMOS RAM,
Compiled by Sub
m Design Rules
V. A. Bachmanov, S. A. Bobrikov, and I. V. Zabolotnov
OAO AngstromM, Moscow
—Temporal characterization is considered of ready circuit topological variants of RAM compilers.
Their number may reach 0.5–10
. The problem is an inappropriate combination of accuracyspeed indica
tors of all known algorithms and software for calculating signal delays, if the specified calculation is performed
for each case directly in the compiler. A number of conceptually related principles are proposed to consider
the precisionperformance ratio within acceptable limits.
CIRCUIT TECHNOLOGY AND DESIGN