1063-7397/02/3101- $27.00 © 2002 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 31, No. 1, 2002, pp. 59–68. Translated from Mikroelektronika, Vol. 31, No. 1, 2002, pp. 66–77.
Original Russian Text Copyright © 2002by Bibilo, Litskevich.
Masterslice VLSIs have made steady progress .
This study deals with the K1574 series, whose mem-
bers have up to 168 leads and 75 thousand gates .
The chips are fabricated in CMOS technology and can
operate at clock rates of up to 50 MHz. There is cur-
rently great interest in the optimization of combina-
tional logic circuits that are to be realized in master-
slices. We have reported a basis method, together with
its software implementation, for the synthesis of multi-
ple-output combinational logic in terms of the K1574
series . The present paper gives an account of a com-
puter-aided evaluation of the basis method and other
synthesis techniques that include different optimization
procedures for different forms of behavioral descrip-
REPRESENTATIONS OF BOOLEAN FUNCTIONS
As is known, a multiple-output combinational cir-
cuit is modeled with completely speciﬁed Boolean
functions . If the circuit has
input terminals and
output terminals, its operation is described by a set of
Boolean functions of
The functions belonging to can be deﬁned in
disjunctive normal form (DNF).
denote a set of Boolean func-
tions deﬁned on
common elementary conjunctions of
the Boolean variables
. We will describe
with two matrices: a ternary matrix
elementary conjunctions of the DNF set
and a Boolean matrix
whose unit entries correspond
to the occurrences of the elementary conjunctions in
the DNFs of the functions. Both
representation of Boolean functions,
we mean their DNF representation. In contrast, the rep-
resentation in the form of parenthesized algebraic
expressions in terms of the AND, OR, and NOT opera-
tors will be called the
Thus, a function set to be implemented in com-
binational logic will be deﬁned as
In this study, logic circuits are assumed to be imple-
mented in the K1574 masterslice series. Each member
of this library is built from a certain number of
on a chip . The K1574 series includes inverters;
multiplexers; buffers; and AND, OR, NAND, NOR,
XOR, biconditional, and more complex gates. The
maximum number of basic cells (15) is taken by the 4-
to-1 inverting multiplexer, but most of the other library
elements require less than 10 cells. Each element
implements one Boolean function. The maximum num-
ber of input terminals (eight) is offered by an AND and
an OR gate, with the majority of the other library ele-
ments having four input terminals at most.
FORMULATION OF THE SYNTHESIS PROBLEM
The problem of logic synthesis within the K1574
series is formulated as follows.
Construct a combinational
that implements a given set of com-
pletely speciﬁed Boolean functions in terms of the
K1574 masterslice series.
In what follows,
means a combinational logic
means a masterslice of the
By deﬁnition, the
of a circuit is the total
number of basic cells required for its implementation.
Synthesis Techniques for Masterslice Combinational Logic:
A Computer-Aided Evaluation
P. N. Bibilo and V. G. Litskevich
Institute of Engineering Cybernetics, National Academy of Sciences of Belarus, Belarus
Received December 26, 2000
—A computer-aided evaluation of certain techniques for combinational-logic synthesis within a mas-
terslice library is presented.