Synthesis and Characterization of Cross-Linked
Nanocomposite as a Gate Dielectric for p-Type Silicon
and SHAHRAM GHASEMI
1.—Department of Solid State Physics, University of Mazandaran, Babolsar 4741695447, Iran.
2.—Faculty of Chemistry, University of Mazandaran, Babolsar, Iran. 3.—e-mail:
A good cross-linking between a povidone–silicon oxide nanocomposite has
been created using a polar solvent. Furthermore, the effect of annealing
temperatures (150°C, 200°C, and 240°C) on the solution-processed povidone–
silicon oxide dielectric ﬁlms has been studied. Fourier transform infrared
spectroscopy and x-ray photoelectron spectroscopy were applied to identify the
chemical interactions of the nanocomposite. Morphology of the thin ﬁlms was
examined using atomic force microscopy. Electrical parameters of ﬁeld effect
transistors (FETs) were calculated on the basis of the information obtained
from current–voltage (I–V) and capacitance–voltage (C–V) measurements in
the metal–insulator–semiconductor structure. Nanocomposite ﬁlms had very
low surface roughness (0.036–0.084 nm). Si-O-Si and Si-O-C covalent bonds as
well as Si-OH hydrogen bonds were formed in the nanocomposite structure.
High hole mobilities (1.15–3.87 cm
) and low leakage current densi-
ties were obtained for the p-type Si FETs. The decrease in the Si-OH hydrogen
bonds in the dielectric ﬁlm annealed at 150°C led to a decrease in capacitance
and leakage current as well as threshold voltage, and resulted in an increase
in mobility and on/off current ratio. By further increasing the annealing
temperatures (200°C and 240°C), the binding energies of all the bonds were
shifted toward lower values. Therefore, it was concluded that many bonds
could have degraded and that defects might have formed in the dielectric ﬁlm
nanostructure leading to a decline in the electrical parameters of the FETs.
Key words: p-Type Si FET, gate dielectric, annealing temperature, leakage
current, charge carrier mobility
Silicon oxide as a gate dielectric has been widely
used in ﬁeld-effect transistors (FET) during the last
Electron mobilities up to
and hole mobilities up to
have been reported for silicon oxide
gate dielectric ﬁlms.
One disadvantage of oxide
silicon dielectric thin ﬁlms is the high leakage
The leakage current densities have
been recorded from 10
the gate voltage between 0 and À 2.5 V f or an l/
/p-type Si structure.
In addition, these
devices are often made using vacuum deposition
methods such as chemical vapor deposition (CVD)
and physical vapor deposition, which require long
pump-down times and increased fabrication
Thus, organic materials have been extensively
studied by many researchers.
ﬁlms can be deposited by solution deposition meth-
ods at room temperature in a few seconds without
using vacuum equipment,
so they are suit-
able for large-area fabrication at a lower cost.
(Received January 23, 2017; accepted March 14, 2018;
published online March 28, 2018)
Journal of ELECTRONIC MATERIALS, Vol. 47, No. 7, 2018
2018 The Minerals, Metals & Materials Society