1063-7397/03/3204- $25.00 © 2003 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 32, No. 4, 2003, pp. 243–246. Translated from Mikroelektronika, Vol. 32, No. 4, 2003, pp. 305–309.
Original Russian Text Copyright © 2003 by Lyul’kin.
As is well known, gate-level modeling cannot cover
certain stuck-at faults in digital circuits built by com-
plementary metal–oxide–semiconductor (CMOS) tech-
nology, the stuck-open (SOP) fault being an example
[1–3]. In fact, experiments have revealed that a consid-
erable proportion of faults found in CMOS logic cannot
be detected with a
test vector generated at the
gate level . Even for combinational circuits, two vec-
tors have to be applied in succession: an initialization
and a sensitization one. This is a serious hindrance to
probabilistic fault-simulation techniques. However,
fairly efﬁcient deterministic methods of test-vector
generation have been developed for SOP faults in true
CMOS circuits [3, 5].
This paper proposes a deterministic method of test-
vector generation for SOP and other faults in CMOS
combinational circuits represented at the switch level.
A feature of our approach is that it allows one to modify
a gate-level test vector so that this apply to all faults of
interest. This might be seen as an important advantage
because switch-level modeling generally leads to mul-
tidimensional combinatorial problems.
FORMULATION OF PROBLEMS
Let us consider a CMOS combinational circuit at the
switch level, the switches representing the transistors.
The faults of interest include the SOP fault, with which
the transistor remains nonconducting whatever its gate
The ﬁgure shows an example switch-level represen-
tation of a circuit implementing the function
denote the input nodes and the
respective input signals;
are the internal
are the switches representing tran-
sistors. Notice that the node
is connected to the out-
put node. The circuit will serve to illustrate the method
At the switch level, n- and p-channel transistors are
modeled with positive and negative switches, respec-
tively. By deﬁnition, a positive switch is closed if and
only if its control terminal is at 1 while a negative
switch is closed if and only if its control terminal is at 0.
We assume that n- and p-channel transistors are used
for closing and opening the paths that connect 0- and
1-sources, respectively, to nodes.
By the structural approach [6, 7], test vectors for a
given fault in a given circuit element are generally gen-
erated in three steps: (1) For the element, identify a
stimulus such that the response would be affected by
the fault. (2) Trace a path through which the response
could reach an output node. (3) Find a set of input val-
ues that could drive internal nodes to logic levels deter-
mined in steps (1) and (2).
The three problems have been treated at the gate
level. We will address them at the switch level.
SOLVING PROBLEM 1:
IDENTIFYING A LOCAL STIMULUS
Consider an SOP fault
that may exist in a positive
be an output node or a node
adjacent to the control terminals of some switches. The
path is deﬁned as a sequence of switches connected in
Let us identify three sets of paths to
: (i) a set
of paths that start from a 0-source (1-source) and pass
, (ii) a set
of paths that start from the same
source but do not pass through
, and (iii) a set
paths from a 1-source (0-source).
The positive (negative) switch
is tested for the
by means of a pair
) of input vectors
Switch-Level Test-Vector Generation
for CMOS Combinational Logic
A. E. Lyul’kin
Belarussian State University, Leningradskaya ul. 14, Minsk, 220080 Belarus
Received June 10, 2002
—A method is proposed of test-vector generation for stuck-open and other faults in CMOS combina-
tional circuits represented at the switch level. It consists in solving three problems: (1) Identify a stimulus that
should be applied to the element under test. (2) Trace a path through which the response could reach an output
node. (3) Find a set of input values that could drive internal nodes to logic levels determined in solving problems (1)
and (2). The method is illustrated with an example.
DEVICES AND CIRCUITS