Switch-Level Test-Vector Generation for CMOS Combinational Logic

Switch-Level Test-Vector Generation for CMOS Combinational Logic A method is proposed of test-vector generation for stuck-open and other faults in CMOS combinational circuits represented at the switch level. It consists in solving three problems: (1) Identify a stimulus that should be applied to the element under test. (2) Trace a path through which the response could reach an output node. (3) Find a set of input values that could drive internal nodes to logic levels determined in solving problems (1) and (2). The method is illustrated with an example. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Switch-Level Test-Vector Generation for CMOS Combinational Logic

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Publisher
Kluwer Academic Publishers-Plenum Publishers
Copyright
Copyright © 2003 by MAIK Nauka/Interperiodica
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1023/A:1024527632636
Publisher site
See Article on Publisher Site

Abstract

A method is proposed of test-vector generation for stuck-open and other faults in CMOS combinational circuits represented at the switch level. It consists in solving three problems: (1) Identify a stimulus that should be applied to the element under test. (2) Trace a path through which the response could reach an output node. (3) Find a set of input values that could drive internal nodes to logic levels determined in solving problems (1) and (2). The method is illustrated with an example.

Journal

Russian MicroelectronicsSpringer Journals

Published: Oct 11, 2004

References

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