One of the most widely used approaches to simulation of complex lithographic systems is considered. The approach makes it possible to take into account the effect of the features of the manufacturing process on the transfer of very large-scale integration (VLSI) topology to a silicon wafer. The approach is based on the present-day aids for simulation and computer-aided design (CAD) of VLSI circuits and provides a means for reducing errors (that arise from the imperfection of the manufacturing process) in transferring the design onto the silicon wafer. A family of empirical VT-5 mathematical models involving a variable threshold is analyzed. The models are used in the CAD Calibre, Mentor Graphics Ltd. The results of calibration and verification of the process model for a polysilicon layer produced by the technology of Department of Microtechnology (DMT), Scientific Research Institute of System Analysis, Russian Academy of Sciences, in compliance with the 0.25 μm design standards are reported. The results of verification of the developed model over the contours of complex topological structures are reported. The verification was conducted with the use of the SEMCal module of the CAD Calibre.
Russian Microelectronics – Springer Journals
Published: Nov 11, 2010
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