ISSN 10637397, Russian Microelectronics, 2012, Vol. 41, No. 2, pp. 132–142. © Pleiades Publishing, Ltd., 2012.
Original Russian Text © S.I. Ol’chev, V.Ya. Stenin, 2012, published in Mikroelektronika, 2012, Vol. 41, No. 2, pp. 146–160.
As their feature sizes are decreased, sub1
grated circuits implemented in complementary
metal–oxide–semiconductor (CMOS) technology
for aerospace applications are known to become more
susceptible to single nuclear particles, particularly to
heavily charged ones, whose impact spot on a die can
be several micrometers across [1, 2]. A need exists for
new approaches to circuit design with the above con
sideration in mind.
For the NOT logic gate, or the inverter, the dual
path approach has been proposed to reduce its suscep
tibility to a singleparticleinduced transient pulse
high enough to exceed the operation threshold [3–7].
In this method, a circuit is designed as two equivalent
paths running from input to output in which every two
corresponding nodes are spaced far enough apart to
prevent them from being affected by the same particle.
Any transient pulse thus constitutes a differential
mode signal, and as such can be detected and rejected.
2. ESSENTIALS OF CMOS
2.1. Circuit Configuration
The susceptibility of dualpath logic gates is esti
mated by considering two copies of a circuit of interest
connected in cascade (a cascade of two flipflops is
subject to positive feedback). Figure 1 illustrates the
case of a CMOS dualpath inverter made up of two
converters, each of which consists of two transistors;
alternatively, the gate terminals of similar transistors
may be connected to each input terminal [3, 6, 7]. The
inverter configuration in Fig. 1 is chosen because it is
much less affected by single particles [6–8]. The first
and the second inverter consist of the converter pair
4, respectively. The dashed lines rep
resent connections that would make the circuit a
flipflop, which forms the core of a DICE static
memory cell [5, 7, 8]. Each converter is a complemen
tarytransistor pair whose gate terminals constitute the
inputs of the converter (shortcircuiting the inputs
would yield a conventional CMOS inverter).
The current sources
transient pulses of photocurrent that are caused by sin
gle nuclear particles and act on an appropriate con
verter. The subscripts 1 and 0 indicate the original logic
level of a converter, referring to its state with a noncon
ducting NMOS transistor and a conducting PMOS
transistor, and vice versa.
With the dualpath approach, the two converters
constitute two paths through an inverter and therefore
must be spaced sufficiently far apart (see Section 1);
otherwise, a transient pulse will contain a common
mode component, which will be treated as a useful sig
nal, possibly causing upsets in the subsequent circuitry.
In the case of memory cells based on
alternating layout of converters is used to maximize
their spacing . Figure 2 shows how to apply the
same method to the circuit configuration of inverters
in Fig. 1. Again, the first and the second inverter con
sist of the converter pair
tively, and the dashed lines represent connections that
would make the circuit a
flipflop. Figure 2 uses a
SingleEventUpset Susceptibility Simulation of Sub1
CMOS DualPath Inverters
S. I. Ol’chev
and V. Ya. Stenin
Research Institute of System Research, Russian Academy of Sciences, Moscow, Russia
National Research Nuclear University (MEPhI), Moscow, Russia
Received March 14, 2011
—A computer simulation is run to estimate the singleeventupset susceptibility of dualpath invert
ers implemented in 0.18
m CMOS technology, which are known to tolerate much higher photocurrent
pulses as compared with conventional designs. Relations are established between the peak photocurrent and
total collected charge associated with a single nuclear particle on the one hand and the peak voltage response
on the other. In the first of two identical inverters connected in cascade, the peak photocurrent is found to be
1.1 to 2.2fold higher than the output current at the instant of extreme output voltage, with the coefficient
depending on the transistor parameters of the inverter. The critical charge to upset is found to be 10 to 15fold
higher than for conventional designs.