Single-event-upset susceptibility simulation of sub-1-μm CMOS dual-path inverters

Single-event-upset susceptibility simulation of sub-1-μm CMOS dual-path inverters A computer simulation is run to estimate the single-event-upset susceptibility of dual-path inverters implemented in 0.18-μm CMOS technology, which are known to tolerate much higher photocurrent pulses as compared with conventional designs. Relations are established between the peak photocurrent and total collected charge associated with a single nuclear particle on the one hand and the peak voltage response on the other. In the first of two identical inverters connected in cascade, the peak photocurrent is found to be 1.1 to 2.2-fold higher than the output current at the instant of extreme output voltage, with the coefficient depending on the transistor parameters of the inverter. The critical charge to upset is found to be 10 to 15-fold higher than for conventional designs. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Single-event-upset susceptibility simulation of sub-1-μm CMOS dual-path inverters

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2012 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S106373971201009X
Publisher site
See Article on Publisher Site

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