ISSN 1063-7397, Russian Microelectronics, 2009, Vol. 38, No. 4, pp. 260–272. © Pleiades Publishing, Ltd., 2009.
Original Russian Text © K.A. Epifantsev, O.A. Gerasimchuk, P.K. Skorobogatov, 2009, published in Mikroelektronika, 2009, Vol. 38, No. 4, pp. 284–301.
Exposure to electromagnetic pulses (EMPs), whether
natural or man-made, is an essential factor in the operation
of modern electronic circuits and systems. With defense-
related hardware, consideration must also be given to
EMPs caused by nuclear explosions [1, 2].
Solid-state parts—discrete semiconductor devices and
integrated circuits (ICs)—do not suffer from the EMP
itself but from the resultant voltage surge . The main
difﬁculty is that such surges can take diverse shapes, being
highly sensitive to the wiring layout, the temporal varia-
tion and the orientation of the electric and magnetic ﬁelds,
the arrangement of adjacent structural members, etc. The
problem thus arises of deﬁning uniform test conditions
that would enable one to predict the hardness of solid-state
parts to electrical overstress (EOS) associated with nuclear
EMPs, allowing their comparison in terms of EOS hard-
The uniform test conditions should cover all typical
EMP surges and the main mechanisms of damage to solid-
state parts as well as allowing one to measure the magni-
tude of exposure and to determine damage thresholds.
2. PREDICTING POSSIBLE CURRENT
OR VOLTAGE SURGES
EMPs are associated with many forms of human activ-
ity; those generated by nuclear explosions are among the
most powerful . In fact, any burst of ionizing radiation
will create an EMP, and therefore an appropriate require-
ment for EMP hardness must always be placed on solid-
state parts intended for defense-related applications.
Nuclear EMPs are characterized by a large radius of action
and high electric and magnetic ﬁelds . EMP radius can
reach tens of kilometers for surface or atmospheric blasts,
and hundreds of kilometers for high-altitude ones. The
electric and magnetic ﬁelds can measure tens of kilovolts
per meter and hundreds of amperes per meter, respec-
EMPs of considerable magnitude are also produced by
lightning strokes. In fact, they can result from lightning-
induced currents as well as from lightning strokes them-
Another important source of EMPs is switching dis-
charges that occur in power electrical equipment .
The EMP hardness of electronic systems has been
found to be mainly determined by that of their solid-state
components . The physical effects involved are classi-
ﬁed as direct or indirect. The former category relates to the
action of an EMP ﬁeld on the charge transport in a semi-
conductor (examples include galvanomagnetic phenom-
ena and ﬁeld effects). The indirect effects are due to surges
of current or voltage that are induced by an EMP in the
wires [6, 7].
When applied to solid-state parts, a nuclear EMP can be
considered a quasi-static ﬁeld because most of the EMP
energy is carried by the spectral components below
which corresponds to a wavelength of about 3 m. Investiga-
tions have shown that the direct effects of such a ﬁeld are
negligible for most purposes if its electric and magnetic
components are less than 100 kV/m and 600 A/m, respec-
tively [2, 7, 8]. Exceptions include long-base magneto-
diodes and magnetotransistors.
Simulating the Exposure of ICs to Voltage Surges
Caused by Nuclear Explosions
K. A. Epifantsev, O. A. Gerasimchuk, and P. K. Skorobogatov
Specialized Electronic Systems (SPELS), Moscow, Russia
Central Institute of Physics and Technology, Russian Federation Ministry of Defence, Sergiev Posad, Moscow oblast, Russia
Received December 16, 2008
—A uniform strategy is developed for testing discrete semiconductor devices and ICs for voltage-
surge hardness, allowing comparison of differing models including ICs of high functional complexity. Perfor-
mance speciﬁcations are deﬁned, justiﬁed, and implemented for a voltage-surge simulator intended for electri-
cal-overstress hardness tests of ICs. On this basis, a test bed is designed and built for evaluating the hardness of
advanced ICs to voltage-surge effects, whether transient or permanent. A procedure is developed for predicting
the electrical-overstress hardness of ICs, which enables one to detect both out-of-tolerance and functional fail-
ures during testing. The procedure and the test setup are validated by experiments with speciﬁc ICs.
DEVICE AND STRUCTURE
MODELING AND SIMULATION