Simulating the exposure of ICs to voltage surges caused by nuclear explosions

Simulating the exposure of ICs to voltage surges caused by nuclear explosions A uniform strategy is developed for testing discrete semiconductor devices and ICs for voltagesurge hardness, allowing comparison of differing models including ICs of high functional complexity. Performance specifications are defined, justified, and implemented for a voltage-surge simulator intended for electrical-overstress hardness tests of ICs. On this basis, a test bed is designed and built for evaluating the hardness of advanced ICs to voltage-surge effects, whether transient or permanent. A procedure is developed for predicting the electrical-overstress hardness of ICs, which enables one to detect both out-of-tolerance and functional failures during testing. The procedure and the test setup are validated by experiments with specific ICs. Russian Microelectronics Springer Journals

Simulating the exposure of ICs to voltage surges caused by nuclear explosions

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SP MAIK Nauka/Interperiodica
Copyright © 2009 by Pleiades Publishing, Ltd.
Engineering; Electrical Engineering
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