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Self-aligned Technology Applied to Planar Power MOSFETs

Self-aligned Technology Applied to Planar Power MOSFETs The self-aligned technology is evaluated by computer simulation in the context of power MOSFET switches. The results enable one to reduce the input and the output capacitance 6- and 12-fold, respectively, with no rise in on-state resistance. The lower capacitances imply a higher switching speed. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Self-aligned Technology Applied to Planar Power MOSFETs

Russian Microelectronics , Volume 32 (1) – Oct 11, 2004

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References (2)

Publisher
Springer Journals
Copyright
Copyright © 2003 by MAIK Nauka/Interperiodica
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
DOI
10.1023/A:1021853617839
Publisher site
See Article on Publisher Site

Abstract

The self-aligned technology is evaluated by computer simulation in the context of power MOSFET switches. The results enable one to reduce the input and the output capacitance 6- and 12-fold, respectively, with no rise in on-state resistance. The lower capacitances imply a higher switching speed.

Journal

Russian MicroelectronicsSpringer Journals

Published: Oct 11, 2004

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