The design of sample-and-hold circuits (SHCs) for pipelined analog-to-digital converters (ADCs) fabricated in CMOS technology is considered. The most important errors in SHCs of various types are analyzed and methods for their reduction are described. Examples of SHCs for a 1.8-V, 20-M sample/s pipelined 0.18-μm-CMOS ADC are presented.
Russian Microelectronics – Springer Journals
Published: Sep 27, 2007
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