ISSN 1063-7397, Russian Microelectronics, 2007, Vol. 36, No. 5, pp. 342–352. © Pleiades Publishing, Ltd., 2007.
Original Russian Text © A.S. Gumenyuk, Yu.I. Bocharov, 2007, published in Mikroelektronika, 2007, Vol. 36, No. 5, pp. 390–400.
Sample-and-hold circuits (SHCs) are intended to
hdd an analog signal value for a certain time required
for the signal processing. These circuits are most
widely used in analog-to-digital converters (ADCs) of
the pipeline type. Figure 1 shows a schematic diagram
of the typical multistage pipelined ADC with 1.5-bit
differential stages, each provided with an SHC.
A broadband input SHC allows the ADC to be used
in an undersampling mode for the conversion of single-
ended signals into differential signals. The SHC param-
eters determine the resolution and dynamical character-
istics of ADCs.
In a view of this critical signiﬁcance of the SHC
parameters, it is important to consider the main princi-
ples of their design, reveal the main sources of errors,
and evaluate the inﬂuence of nonideality of compo-
nents on the ﬁnal accuracy of SHCs.
THE BASE SHC DESIGN
AND THE MAIN SOURCES OF ERRORS
A scheme depicted in Fig. 2 serves a base for all
other SHC conﬁgurations, but it is never used as such in
ADCs because of insufﬁcient accuracy. The most
important sources of errors are as follows.
(i) The CMOS switch introduces nonlinear distor-
tions into the output signal, since its conductivity in the
closed state depends on the input signal level as
Sample-and-Hold Circuits for High-Speed A/D Converters
A. S. Gumenyuk and Yu. I. Bocharov
Moscow Engineering Physics Institute (State University), Moscow, 115409 Russia
Received March 20, 2007
—The design of sample-and-hold circuits (SHCs) for pipelined analog-to-digital converters (ADCs)
fabricated in CMOS technology is considered. The most important errors in SHCs of various types are analyzed
and methods for their reduction are described. Examples of SHCs for a 1.8-V, 20-M sample/s pipelined
m-CMOS ADC are presented.
PACS numbers: 84.30.Vn
Resolution: 1.5 bit
Digital error correction circuit and interface
K1 K2 K3 K
Schematic diagram of the typical pipelined ADC illustrating the use of SHCs.