Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on FPGA

Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on... Wireless Pers Commun https://doi.org/10.1007/s11277-018-5889-9 Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on FPGA 1 2 3 • • • Deepak Kumar Gupta Vijay Kumar Gupta Mahesh Chandra Gaurav Verma Springer Science+Business Media, LLC, part of Springer Nature 2018 Abstract In recent years, the real time hardware implementation of LMS based adaptive noise cancellation on FPGA is becoming popular. There are several works reported in this area in the literature. However, NLMS based implementation of adaptive noise cancella- tion on FPGA using Xilinx System Generator (XSG) is not reported. This paper explores the various forms of parallel architecture based on NLMS algorithm and its hardware implementation on FPGA using XSG for noise minimization from speech signals. In total, the direct form, binary tree direct form and transposed form of parallel architecture of normalized least mean square (NLMS), delayed normalized least mean square and retimed delayed normalized least mean square algorithms are implemented on FPGA using hard- ware co-simulation model. The performance parameters (SNR and MSE) of these algo- rithms are analyzed for the adaptive noise cancellation system and the comparison is made with parallel architectures of least mean square (LMS), delayed least mean square, and retimed http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Wireless Personal Communications Springer Journals

Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on FPGA

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Publisher
Springer US
Copyright
Copyright © 2018 by Springer Science+Business Media, LLC, part of Springer Nature
Subject
Engineering; Communications Engineering, Networks; Signal,Image and Speech Processing; Computer Communication Networks
ISSN
0929-6212
eISSN
1572-834X
D.O.I.
10.1007/s11277-018-5889-9
Publisher site
See Article on Publisher Site

Abstract

Wireless Pers Commun https://doi.org/10.1007/s11277-018-5889-9 Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on FPGA 1 2 3 • • • Deepak Kumar Gupta Vijay Kumar Gupta Mahesh Chandra Gaurav Verma Springer Science+Business Media, LLC, part of Springer Nature 2018 Abstract In recent years, the real time hardware implementation of LMS based adaptive noise cancellation on FPGA is becoming popular. There are several works reported in this area in the literature. However, NLMS based implementation of adaptive noise cancella- tion on FPGA using Xilinx System Generator (XSG) is not reported. This paper explores the various forms of parallel architecture based on NLMS algorithm and its hardware implementation on FPGA using XSG for noise minimization from speech signals. In total, the direct form, binary tree direct form and transposed form of parallel architecture of normalized least mean square (NLMS), delayed normalized least mean square and retimed delayed normalized least mean square algorithms are implemented on FPGA using hard- ware co-simulation model. The performance parameters (SNR and MSE) of these algo- rithms are analyzed for the adaptive noise cancellation system and the comparison is made with parallel architectures of least mean square (LMS), delayed least mean square, and retimed

Journal

Wireless Personal CommunicationsSpringer Journals

Published: Jun 5, 2018

References

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