Single-event upsets and latchups, whose removal is the subject of designing fault- tolerant VLSI and VLSI-based equipment, are the main effects of VLSI exposure to atmospheric neutrons. For a comparative analysis of the fault tolerance of CMOS structures with various design standards, we have investigated domestic and foreign CMOS VLSI with design standards from 0.5 to 0.13 μm and additionally produced test structures of submicron SRAMs with design standards of 0.5, 0.35, and 0.18 μm. The SOI CMOS technology provides the highest efficiency among the design-technological methods. There are no latchups in the specimens of test structures with design standards of 0.5 and 0.35 μm exposed to 250-MeV and 1-GeV protons. We recommend developing the basic components of submicron VLSI with an enhanced resistance to atmospheric neutrons based on techniques that include the typical SEU cross sections and the thyristor- effect cross sections obtained here for CMOS VLSI with various design standards.
Russian Microelectronics – Springer Journals
Published: Jan 8, 2009
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