Prospects for using submicron CMOS VLSI in fault-tolerant equipment operating under exposure to atmospheric neutrons

Prospects for using submicron CMOS VLSI in fault-tolerant equipment operating under exposure to... Single-event upsets and latchups, whose removal is the subject of designing fault- tolerant VLSI and VLSI-based equipment, are the main effects of VLSI exposure to atmospheric neutrons. For a comparative analysis of the fault tolerance of CMOS structures with various design standards, we have investigated domestic and foreign CMOS VLSI with design standards from 0.5 to 0.13 μm and additionally produced test structures of submicron SRAMs with design standards of 0.5, 0.35, and 0.18 μm. The SOI CMOS technology provides the highest efficiency among the design-technological methods. There are no latchups in the specimens of test structures with design standards of 0.5 and 0.35 μm exposed to 250-MeV and 1-GeV protons. We recommend developing the basic components of submicron VLSI with an enhanced resistance to atmospheric neutrons based on techniques that include the typical SEU cross sections and the thyristor- effect cross sections obtained here for CMOS VLSI with various design standards. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Prospects for using submicron CMOS VLSI in fault-tolerant equipment operating under exposure to atmospheric neutrons

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2009 by MAIK Nauka
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739709010053
Publisher site
See Article on Publisher Site

Abstract

Single-event upsets and latchups, whose removal is the subject of designing fault- tolerant VLSI and VLSI-based equipment, are the main effects of VLSI exposure to atmospheric neutrons. For a comparative analysis of the fault tolerance of CMOS structures with various design standards, we have investigated domestic and foreign CMOS VLSI with design standards from 0.5 to 0.13 μm and additionally produced test structures of submicron SRAMs with design standards of 0.5, 0.35, and 0.18 μm. The SOI CMOS technology provides the highest efficiency among the design-technological methods. There are no latchups in the specimens of test structures with design standards of 0.5 and 0.35 μm exposed to 250-MeV and 1-GeV protons. We recommend developing the basic components of submicron VLSI with an enhanced resistance to atmospheric neutrons based on techniques that include the typical SEU cross sections and the thyristor- effect cross sections obtained here for CMOS VLSI with various design standards.

Journal

Russian MicroelectronicsSpringer Journals

Published: Jan 8, 2009

References

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