1063-7397/04/3303- © 2004 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 33, No. 3, 2004, pp. 188–194. Translated from Mikroelektronika, Vol. 33, No. 3, 2004, pp. 233–239.
Original Russian Text Copyright © 2004 by Losev, Starosel’skii.
The microelectronics industry is deeply interested
in developing new methods for the reduction of power
consumption in digital logic. An innovative solution to
the problem is based on thermodynamic reversibility
[1–3]. This strategy is implemented in adiabatic logic
gates using pulsed power delivery. With rising supply
voltage, such a gate performs logical operations while
drawing power from the supply; with falling supply
voltage, the power supply receives most of the
energy that has been stored in the reactors of the gate
during the pulse-rise period. Thus, information is
produced at the former phase of clock cycle and is
deleted at the latter.
Although it is not feasible to completely eliminate
dissipation, this can be reduced to any desired extent by
decreasing the rate of change of supply voltage, sacri-
ﬁcing the rate with which information is produced. The
adiabatic logic in which dissipation is only due to non-
zero rate of change of supply voltage and can be made
as low as desired is called
Valiev and Starosel’skii  have shown that such
logic gates must be as follows:
(i) A gate has three states: a zero state 0, a unity state
1, and a released state
, the third one corresponding to
the minimum output energy.
(ii) The input of a gate is set only when the gate is in
(iii) An input signal remains at the same logic level
over the whole clock cycle of the gate.
(iv) In a gate, every transistor may go to the on state
only at zero drain–source voltage.
(v) In a system of gates, there are no feedback loops
of feedback factor larger than the critical level inside
every gate and between the gates.
Ideally, power consumption must be zero when the
gate is in a quiescent state. In reality, spurious currents
represent a lower limit of power consumption.
It is commonly accepted that
is the energy dissipation per clock cycle and
is the length of a supply-pulse edge [1, 5, 6].
are the best understood type
of adiabatic gate. However, they implement thermody-
namic reversibility only to some extent. A review and a
categorization of quasi-adiabatic gates were given by
With quasi-adiabatic logic, the lowest power con-
sumption is offered by 2n–2n2p static gates  and by
dynamic ones known as efﬁcient charge-recovery logic
(ECRL) , which are built in the complementary
metal–oxide–semiconductor (CMOS) technology.
These gates have three states owing to simultaneous use
of true and inverted signals. On the other hand, the
input signal is lost during the pulse-fall period of supply
voltage, and the rest of the ﬁve conditions are not satis-
ﬁed at all. Accordingly, the minimum energy dissipa-
tion per clock cycle is
is the absolute value of the threshold voltages
for the n- and p-channel transistors, respectively,
is the total capacitance of the logic gate .
The power consumption of the 2n–2n2p and the
ECRL gate was investigated in our previous study .
It has been established that
tends to zero (
= 1 at most. It was also shown that
< 1 is due
to the nonlinear behavior of the transistor channel resis-
tance through which the capacitors are charged and dis-
Power Consumption of Asymptotically
Adiabatic Static Logic Gates
V. V. Losev and V. I. Starosel’skii
Moscow State Institute of Electronic Engineering (Technical University), Moscow, Russia
Received April 14, 2003
—A computer simulation is conducted of power consumption in the 1n–1p type of asymptotically adi-
abatic static logic gate. The increase is estimated in dissipation due to violation of any single condition of ther-
modynamic reversibility. The dissipation characteristics obtained are compared with those of quasi-adiabatic
gates of the 2n–2n2p and the efﬁcient charge-recovery logic (ECRL) type.