Peculiarities of three-dimensional simulation of SOI MOS transistors with an indirect gate

Peculiarities of three-dimensional simulation of SOI MOS transistors with an indirect gate A methodology for a three-dimensional (3D) simulation of submicron SOI MOS transistors, taking into account a lithographic topology distortion, is presented. The peculiarities of constructing a 3D structure are considered. An efficient method for grid generation is proposed. The results of simulating O-type SOI MOS transistors with and without precorrection of topology are given. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Peculiarities of three-dimensional simulation of SOI MOS transistors with an indirect gate

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Publisher
Springer Journals
Copyright
Copyright © 2012 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739712010040
Publisher site
See Article on Publisher Site

Abstract

A methodology for a three-dimensional (3D) simulation of submicron SOI MOS transistors, taking into account a lithographic topology distortion, is presented. The peculiarities of constructing a 3D structure are considered. An efficient method for grid generation is proposed. The results of simulating O-type SOI MOS transistors with and without precorrection of topology are given.

Journal

Russian MicroelectronicsSpringer Journals

Published: Mar 28, 2012

References

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