A methodology for a three-dimensional (3D) simulation of submicron SOI MOS transistors, taking into account a lithographic topology distortion, is presented. The peculiarities of constructing a 3D structure are considered. An efficient method for grid generation is proposed. The results of simulating O-type SOI MOS transistors with and without precorrection of topology are given.
Russian Microelectronics – Springer Journals
Published: Mar 28, 2012
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