1063-7397/05/3401- © 2005 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 34, No. 1, 2005, pp. 22–29. Translated from Mikroelektronika, Vol. 34, No. 1, 2005, pp. 27–36.
Original Russian Text Copyright © 2005 by Gorlov, Emel’yanov, Rubtsevich, Smirnov.
Electrostatic discharge (ESD) may produce two
types of fault in solid-state parts [1, 2]. With a tolerable
fault, the overall performance of the part remains
within the speciﬁcations. An intolerable fault results in
a complete failure.
ESD-induced tolerable faults may be divided into
three categories according to their effect on the reliabil-
ity of the solid-state part:
(i) The useful life of the solid-state part remains the
(ii) Some of the performance parameters deviate
insigniﬁcantly from the speciﬁcations, and the useful
life is likely to be shortened.
(iii) Some of the performance parameters go well
beyond the speciﬁed tolerances, and the reliability of
the part is seriously reduced.
[3–5] ﬁrst discovered annealing of
ESD-induced tolerable faults under temporary expo-
sure to elevated temperatures or electrical stress; it may
also occur at room temperature. The phenomenon
should be connected with the nature of ESD effects:
trap generation at the Si/SiO
interface, charge buildup
in the oxide, ESD-induced mechanical stress, etc.
Figure 1 illustrates the above by representing the
annealing dynamics of KT315B silicon bipolar junc-
tion transistors (BJTs) observed in an experiment. The
graphs depict the percentage change in the common-
emitter forward current transfer ratio
as a function of
time under thermal annealing at 125
C, with ESD hav-
ing been applied to the base. Curves
that the stronger the ESD damage is, the smaller the
amount of annealing. In fact, annealing will not be
observed if the parameter is changed by a large amount,
as evidenced by curve
. Notice also that annealing is
most rapid over the ﬁrst ten hours, disappearing in the
Other experiments also revealed that electrical and
thermal stress applied in combination tend to encour-
age annealing, as in reliability testing.
The experimental data obtained might be interpreted
as follows. If the magnitude of ESD is below a certain
level, the resultant moderate amount of performance
degradation should be linked, e.g., to a change in inter-
face-trap density and to trap generation in the active
region: these effects alter the number of free carriers
involved in electrical conduction. The smaller the ESD-
induced damage, the more likely is complete recovery
of the device under annealing.
IC SCREENING FOR ESD SUSCEPTIBILITY
When tolerance to ESD is a requirement, it may be
wise to introduce screening for ESD susceptibility into
integrated-circuit (IC) manufacture. To this end, Gorlov
[6, 7] proposed a screening procedure that con-
sists in measuring the effect of a single voltage pulse on
one or more IC parameters, the magnitude of the pulse
being such as to allow thermal-annealing recovery. The
IC parameters to be measured will be referred to as
Parts Screening for ESD Susceptibility
M. I. Gorlov*, V. A. Emel’yanov**, I. I. Rubtsevich**, and D. Yu. Smirnov*
* Voronezh State Technical University, Voronezh, Russia
** NPO Integral
Received March 26, 2004
—An approach to screening of ICs and discrete transistors for ESD susceptibility is discussed. Proce-
dures are proposed for comparing transistor batches in terms of reliability and for identifying items of unusual
reliability among conforming ones in an IC batch, using annealing of ESD-induced faults.
MATERIALS AND MICROSTRUCTURE
40 60 80 1000
Example annealing dynamics of BJTs.