Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators

Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators In recent years, image processing has been a key application area for mobile and embedded computing platforms. In this context, many-core accelerators are a viable solution to efficiently execute highly parallel kernels. However, architectural constraints impose hard limits on the main memory bandwidth, and push for software techniques which optimize the memory usage of complex multi-kernel applications. In this work, we propose a set of techniques, mainly based on graph analysis and image tiling, targeted to accelerate the execution of image processing applications expressed as standard OpenVX graphs on cluster-based many-core accelerators. We have developed a run-time framework which implements these techniques using a front-end compliant to the OpenVX standard, and based on an OpenCL extension that enables more explicit control and efficient reuse of on-chip memory and greatly reduces the recourse to off-chip memory for storing intermediate results. Experiments performed on the STHORM many-core accelerator demonstrate that our approach leads to massive reduction of time and bandwidth, even when the main memory bandwidth for the accelerator is severely constrained. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Journal of Real-Time Image Processing Springer Journals

Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators

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Publisher
Springer Berlin Heidelberg
Copyright
Copyright © 2015 by Springer-Verlag Berlin Heidelberg
Subject
Computer Science; Image Processing and Computer Vision; Multimedia Information Systems; Computer Graphics; Pattern Recognition; Signal,Image and Speech Processing
ISSN
1861-8200
eISSN
1861-8219
D.O.I.
10.1007/s11554-015-0544-0
Publisher site
See Article on Publisher Site

Abstract

In recent years, image processing has been a key application area for mobile and embedded computing platforms. In this context, many-core accelerators are a viable solution to efficiently execute highly parallel kernels. However, architectural constraints impose hard limits on the main memory bandwidth, and push for software techniques which optimize the memory usage of complex multi-kernel applications. In this work, we propose a set of techniques, mainly based on graph analysis and image tiling, targeted to accelerate the execution of image processing applications expressed as standard OpenVX graphs on cluster-based many-core accelerators. We have developed a run-time framework which implements these techniques using a front-end compliant to the OpenVX standard, and based on an OpenCL extension that enables more explicit control and efficient reuse of on-chip memory and greatly reduces the recourse to off-chip memory for storing intermediate results. Experiments performed on the STHORM many-core accelerator demonstrate that our approach leads to massive reduction of time and bandwidth, even when the main memory bandwidth for the accelerator is severely constrained.

Journal

Journal of Real-Time Image ProcessingSpringer Journals

Published: Nov 20, 2015

References

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