ISSN 10637397, Russian Microelectronics, 2012, Vol. 41, No. 3, pp. 213–219. © Pleiades Publishing, Ltd., 2012.
Original Russian Text © A.O. Vlasov, B.E. Evlampiev, P.G. Kirichenko, A.A. Kochnov, 2012, published in Mikroelektronika, 2012, Vol. 41, No. 3, pp. 233–240.
Companies developing computeraided design
(CAD) programs currently offer a broad spectrum of
products both for accomplishing individual stages of
the design flow for chips of a specific class and for the
entire design flow. These flows are universal and
intended for a wide range of digital integrated circuits.
They represent a sequence of steps and corresponding
batch files for accomplishing designing. However, the
chips can differ in some parameters, the main ones
being the architectural complexity (the number of
devices on a crystal intended for different purposes),
the maximum operating frequency, the power con
sumption, and the crystal area. As a rule, the existing
CADs have the flows developed in detail for optimiza
tion of one or two of the above parameters. In the case
of a large project (a system on a crystal) when all
parameters are critical, the greater part of the work on
developing the optimal flow and successful designing
falls on the developers.
The K64RIO microprocessor is one of such chips.
The following key peculiarities and components of this
chip should be distinguished.
1. A kernel of a 64bit microprocessor.
2. 250 MHz operating frequency of the kernel.
3. USB 2.0.
4. Ethernet 100/100 Mbit/s.
5. DDR SDRAM, 64bit 166/320 MHz, parity
6. PCI, 32 bit 66 MHz.
7. Parallel RapidIO 500 Mbit/s.
8. Serial RapidIO (4 channels 1.25 Gbit/s each).
9. FLASH, COMport.
10. A large number of custom blocks (register files,
RapidIP and DDR SDRAM receivers/transmitters,
frequency synthesizer, phase lock).
m manufacturing technology.
mm in size.
The use of the standard design flow does not allow
reaching the required parameters, first of all, concern
ing operating speed. In order to solve these problems,
substantial changes were introduced into the design
flow and original techniques were applied.
2. METHODS FOR OPTIMIZATION
OF THE AREA OF MICROPROCESSOR
BLOCKS WITH PRESERVATION
Improvement of the timing data of a functional
block is the toppriority problem of any developer.
However, it often happens that a device does not only
lose its performance at the layout design stage but also
turns out to be unfeasible to implement: the high den
sity of the element placement hinders the routing of
intercircuit connections . As a rule, the block
boundaries on the crystal are strictly specified and an
increase in the performance yields an increase in the
total area of the block cells and, as a result, the density
of their placement . By the example of the floating
point block (FPU) of the K64RIO microprocessor,
the following approaches to the optimization of the
design area without deterioration of performance were
1. Replacing of custom fastspeed triggers in non
critical circuits with standard library ones.
Optimization of the Design Flow of the System on a K64RIO Crystal
Manufactured Using the 0.18
A. O. Vlasov, B. E. Evlampiev, P. G. Kirichenko, and A. A. Kochnov
ScientificResearch Institute for System Studies, Russian Academy of Science, Russia
email: firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com
Received March 18, 2011
—In the process of developing a highperformance system on a crystal, the standard design flow pro
posed by CAD suppliers has been substantially changed and expanded due to the application of new design
methods and the use of independently developed custom blocks. These changes made it possible to solve the
following important problems: optimization of the area, with the performance at the stage of synthesis being
preserved up to 20%, which improves the quality of the placement and design routability during layout design
ing; construction of a power grid providing a voltage drop not greater than 6.6% of the rated voltage; automa
tion of the process of reaching the required performance and optimization of a number of layout stages yield
ing a decrease by a factor of 2–3 in the time of routing and improving the design quality from the standpoint
of such parameters as noise immunity and performance.