Optimization of the design flow of the system on a K64-RIO crystal manufactured using the 0.18 μm technology

Optimization of the design flow of the system on a K64-RIO crystal manufactured using the 0.18... In the process of developing a high-performance system on a crystal, the standard design flow proposed by CAD suppliers has been substantially changed and expanded due to the application of new design methods and the use of independently developed custom blocks. These changes made it possible to solve the following important problems: optimization of the area, with the performance at the stage of synthesis being preserved up to 20%, which improves the quality of the placement and design routability during layout designing; construction of a power grid providing a voltage drop not greater than 6.6% of the rated voltage; automation of the process of reaching the required performance and optimization of a number of layout stages yielding a decrease by a factor of 2–3 in the time of routing and improving the design quality from the standpoint of such parameters as noise immunity and performance. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Optimization of the design flow of the system on a K64-RIO crystal manufactured using the 0.18 μm technology

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2012 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739712020096
Publisher site
See Article on Publisher Site

Abstract

In the process of developing a high-performance system on a crystal, the standard design flow proposed by CAD suppliers has been substantially changed and expanded due to the application of new design methods and the use of independently developed custom blocks. These changes made it possible to solve the following important problems: optimization of the area, with the performance at the stage of synthesis being preserved up to 20%, which improves the quality of the placement and design routability during layout designing; construction of a power grid providing a voltage drop not greater than 6.6% of the rated voltage; automation of the process of reaching the required performance and optimization of a number of layout stages yielding a decrease by a factor of 2–3 in the time of routing and improving the design quality from the standpoint of such parameters as noise immunity and performance.

Journal

Russian MicroelectronicsSpringer Journals

Published: May 4, 2012

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