Optimization of parameters of double-gate sub-20 nanometers SOI CMOS transistors with architecture “without overlapping”

Optimization of parameters of double-gate sub-20 nanometers SOI CMOS transistors with... One of the possible approaches of an optimum choice of topological parameters of double-gate sub-20 nm CMOS transistors with a silicon-on-insulator structure and architecture that is “without an over-lapping” gate—the extended drain/source areas for minimization of short-channel effects—is discussed. The characteristics of inverters on transistors with a channel length of 16 nm for high-speed applications and applications with a low level of static power are numerically investigated in the power supply voltage range from 0.4 V up to 1 V. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Optimization of parameters of double-gate sub-20 nanometers SOI CMOS transistors with architecture “without overlapping”

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2012 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739711060084
Publisher site
See Article on Publisher Site

Abstract

One of the possible approaches of an optimum choice of topological parameters of double-gate sub-20 nm CMOS transistors with a silicon-on-insulator structure and architecture that is “without an over-lapping” gate—the extended drain/source areas for minimization of short-channel effects—is discussed. The characteristics of inverters on transistors with a channel length of 16 nm for high-speed applications and applications with a low level of static power are numerically investigated in the power supply voltage range from 0.4 V up to 1 V.

Journal

Russian MicroelectronicsSpringer Journals

Published: Jan 8, 2012

References

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