Operability analysis of submicron CMOS-based VLSI RAMs operated under extreme thermal conditions

Operability analysis of submicron CMOS-based VLSI RAMs operated under extreme thermal conditions Variations in the characteristics of the memory cells of submicron CMOS RAMs caused by changes in temperature were simulated and experimentally investigated in a wide temperature range of minus 50°C to +150°C. It was found that submicron VLSI circuits fabricated on the basis of the 0.35-μm bulk-CMOS technology with epitaxial layers and of the industrial 0.18-μm bulk-CMOS technology are, in the large, characterized by high maximum permissible temperatures. The simulation results were confirmed by the tests of submicron 0.35- and 0.18-μm CMOS RAMs based, respectively, on 6-transistor and 12-transistor memory cells with heavy-ion tolerant (HIT) and dual interlocked storage-cell (DICE) structures. The results of the investigation allow one to make a reasoned selection of memory cells to be used in practical embodiments of VLSI static RAMs intended to operate under extreme conditions http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Operability analysis of submicron CMOS-based VLSI RAMs operated under extreme thermal conditions

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Publisher
Springer Journals
Copyright
Copyright © 2009 by MAIK Nauka
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739709010065
Publisher site
See Article on Publisher Site

Abstract

Variations in the characteristics of the memory cells of submicron CMOS RAMs caused by changes in temperature were simulated and experimentally investigated in a wide temperature range of minus 50°C to +150°C. It was found that submicron VLSI circuits fabricated on the basis of the 0.35-μm bulk-CMOS technology with epitaxial layers and of the industrial 0.18-μm bulk-CMOS technology are, in the large, characterized by high maximum permissible temperatures. The simulation results were confirmed by the tests of submicron 0.35- and 0.18-μm CMOS RAMs based, respectively, on 6-transistor and 12-transistor memory cells with heavy-ion tolerant (HIT) and dual interlocked storage-cell (DICE) structures. The results of the investigation allow one to make a reasoned selection of memory cells to be used in practical embodiments of VLSI static RAMs intended to operate under extreme conditions

Journal

Russian MicroelectronicsSpringer Journals

Published: Jan 8, 2009

References

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