1063-7397/03/3206- $25.00 © 2003 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 32, No. 6, 2003, pp. 339–346. Translated from Mikroelektronika, Vol. 32, No. 6, 2003, pp. 421–429.
Original Russian Text Copyright © 2003 by Plekhanov.
The automated synthesis of standard-cell layout
essentially involves routing. With submicrometer fea-
ture sizes and high switching speeds, routing proce-
dures should comply with constraints on delay and
electrical parameters such as the resistance and capaci-
tance of a wiring segment, the allowable number of vias
to polysilicon, and the allowable number of transistors
in parallel or in series.
FORMULATION OF THE PROBLEM
Routing is usually classiﬁed as being global or
detailed. Global routing mostly yields an outline net
conﬁguration, whereas detailed routing deals with indi-
vidual circuit fragments, such as standard cells, and
should result in a precise layout. On a general level, a
routing problem is stated as follows: Given a list of nets
and a list of obstacles, i.e., areas forbidden to wiring
paths. For each net from the list, ﬁnd a set of wiring
paths that connect the pads of the net in such a way that
the paths do not cross each other and the obstacles, sub-
ject to certain constraints on the electrical characteris-
tics of the resultant wiring.
In general, standard-cell routing has the following
(1) A standard cell is speciﬁed in terms of cell
height, the conﬁguration and dimensions of ground and
power lines, the connection of ﬁeld-effect transistors
(FETs) to the lines, etc.
(2) Routing embraces two or more layers (including
a polysilicon one) and is layer-speciﬁc; for example,
the use of the second metallization layer may be
(3) The arrangement of pads to be interconnected is
determined by that of FETs, which are to be treated as
obstacles (Fig. 1).
(4) Routing deals with a loose layout and so is fol-
lowed by layout compaction  and wire-length mini-
(5) Some nets require special routing; examples are
ground and power nets.
With submicrometer feature sizes, additional con-
straints are placed on routing:
(1) Pads through which a high current may pass
must be connected by metal, not polysilicon (Fig. 2).
Such pads are usually FET source or drain electrodes.
Figure 3 presents the graphical symbols that we use for
different types of track and via.
(2) A limit is set on the number of FETs in series that
, by which we mean a pad that
provides contact to the source or drain of a FET or to an
external circuit (Fig. 4).
(3) Similarly, there is a limit to the number of FETs
in parallel that share a current source (Fig. 5).
(4) If a path runs in a layer of high resistivity and
capacitance, the path length is limited (such a layer is
(5) If a path runs in a metal layer, the path should not
pass over a gate region belonging to a different net.
In light of the above, we consider this routing prob-
lem: For each net, ﬁnd a set of wiring paths that connect
the pads of the net in such a way that the segments of
resultant wiring do not cross each other and the obsta-
cles, subject to the constraints on segments and nets as
deﬁned above (the problem is understood to cover
ground and power nets as well).
FOR STANDARD-CELL ROUTING
It is common practice to perform standard-cell rout-
ing by the Lee algorithm . Although this strategy is
relatively simple and often yields a complete solution,
it has its limitations:
(1) Nets are processed in turn, and the order in
which they are taken must be set beforehand; in doing
so, one has to ensure that the paths deﬁned at each rout-
ing stage leave room for remaining stages.
(2) Routing ignores electrical constraints.
New Method for Standard-Cell Routing Subject
to Electrical Constraints
A. S. Plekhanov
Motorola Moscow Research Laboratory, Moscow, Russia
Received December 26, 2002
—A method is proposed for standard-cell routing subject to electrical constraints. It enables one to
perform wire planning and detailed routing simultaneously.