ISSN 1063-7397, Russian Microelectronics, 2008, Vol. 37, No. 3, pp. 201–212. © Pleiades Publishing, Ltd., 2008.
Original Russian Text © P.N. Bibilo, V.I. Romanov, 2008, published in Mikroelektronika, 2008, Vol. 37, No. 3, pp. 228–240.
Combinational-logic synthesis is a part of the over-
all task of designing digital devices and systems, which
is performed within an end-to-end computer-aided-
design (CAD) system that converts an algorithm into a
circuit layout. End-to-end CAD is sometimes named
as contrasted with
CAD intended to
fulﬁll tasks of the same design level, such as logic syn-
thesis . Effectively, horizontal CAD systems repre-
sent a new stage in design automation, where emphasis
is placed on the efﬁciency of designs generated.
This paper describes the results of experiments with
horizontal CAD tools. It is shown that combined use of
several such systems provides a more effective
approach to the synthesis of irregular logic circuits
within various design libraries.
ITERATIVE SYNTHESIS OF LOGIC CIRCUITS
Synthesis of very-large-scale-integration (VLSI)
logic circuits within a user library can be performed in
different synthesizers, LeonardoSpectrum , or sim-
ply Leonardo, being among the most common ones.
The user library may be intended for application-spe-
ciﬁc integrated circuits (ASICs) or semicustom cir-
cuits, such as gate arrays. In addition, Leonardo can be
used to synthesize ﬁeld-programmable gate arrays
(FPGAs) and complex programmable logic devices
Below, the word
is used to denote
LeonardoSpectrum. The synthesizer can optimize cir-
cuits for area or delay and can take into account various
process-technology limitations. An algorithmic descrip-
tion in VHDL is generally used as input data. Circuit
synthesis is divided into two stages: high-level synthe-
sis, also known as preoptimization, yielding a register-
transfer-level (RTL) description and technology map-
ping . An advantage of the synthesizer concerned is
that it can derive an RTL description from a structural
description of a synthesized logic circuit, using the
instruction. An RTL description so obtained will
be denoted by
equivalent to the input VHDL description.
used to synthesize another version of the gate array or
FPGA; experience shows that the newer version may
well perform better and be less complex than the one
designed from the original VHDL description. This
strategy is called
It does not, how-
ever, ensure a reduction in circuit complexity in every
case. Nevertheless, special algorithms have been pro-
posed to transform RTL descriptions in a manner such
that the resultant circuit is likely to be less complex, as
observed in experiments on gate-array synthesis .
The algorithms will be referred to as grouping algo-
Below we report the results of further experiments
with grouping algorithms. The reasons for this investi-
gation are as follows:
(1) Programs implementing grouping algorithms
have been included in a CAD system . This required
evaluation of grouping algorithms in the context of
multilevel representations of functions, in addition to
doing so for two-level OR/AND representations .
(2) It is important to evaluate grouping algorithms in
relation to FPGA synthesis.
(3) It is of interest to test iterative synthesis on two
identical libraries or two different libraries taken in any
order, and compare the results. Encouraging evidence
had been obtained in the case of a gate-array and an
(4) The gate-array library used in the previous study
 had been modiﬁed to improve the accuracy of gate
delay to the picosecond range.
New Experiments on Iterative Synthesis
of Combinational Circuits
P. N. Bibilo and V. I. Romanov
Joint Institute of Problems of Information Science, National Academy of Sciences of Belarus, Minsk, Belarus
Received May 15, 2007
—A new strategy is presented for experiments on iterative synthesis of combinational circuits within
a gate-array or an FPGA library. Results thus obtained are presented. Reductions in circuit complexity are
achieved with each of the libraries.