A new manufacturing process is proposed and evaluated for CMOS memory circuits that is designed to decrease labor input and to increase yield. It essentially uses thermal silicon dioxide instead of silicon nitride as the material of the mask for n −- and p −-wells, and employs an improved doping procedure for the wells. The new process is shown to decrease considerably the residual stress and defect density in the wafer. Its advantages over the standard process are supported by a two-dimensional computer simulation with Silvaco’s SSUPREM4.
Russian Microelectronics – Springer Journals
Published: May 27, 2008
It’s your single place to instantly
discover and read the research
that matters to you.
Enjoy affordable access to
over 18 million articles from more than
15,000 peer-reviewed journals.
All for just $49/month
Query the DeepDyve database, plus search all of PubMed and Google Scholar seamlessly
Save any article or search result from DeepDyve, PubMed, and Google Scholar... all in one place.
All the latest content is available, no embargo periods.
“Whoa! It’s like Spotify but for academic articles.”@Phil_Robichaud