New CMOS process using a thermal-oxide mask for making n −- and p −-Wells

New CMOS process using a thermal-oxide mask for making n −- and p −-Wells A new manufacturing process is proposed and evaluated for CMOS memory circuits that is designed to decrease labor input and to increase yield. It essentially uses thermal silicon dioxide instead of silicon nitride as the material of the mask for n −- and p −-wells, and employs an improved doping procedure for the wells. The new process is shown to decrease considerably the residual stress and defect density in the wafer. Its advantages over the standard process are supported by a two-dimensional computer simulation with Silvaco’s SSUPREM4. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

New CMOS process using a thermal-oxide mask for making n −- and p −-Wells

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Publisher
SP MAIK Nauka/Interperiodica
Copyright
Copyright © 2008 by MAIK Nauka
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739708030049
Publisher site
See Article on Publisher Site

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