ISSN 10637397, Russian Microelectronics, 2011, Vol. 40, No. 2, pp. 119–127. © Pleiades Publishing, Ltd., 2011.
Original Russian Text © V.V. Shubin, 2011, published in Mikroelektronika, 2011, Vol. 40, No. 2, pp. 130–139.
The adder is a major building block of highspeed
digital circuits that continues to attract a great deal of
research interest for the following reasons:
Addition is part of other major operations such as
subtraction, multiplication, division, and exponentia
The speed of a digital signal processor or a central
processing unit is strongly dependent on the perfor
mance of the adder it contains .
Any arithmetic/logic unit includes an adder as its
major component [5, 6].
Adders play an important part in the final phase of
signal processing in some advanced architectures of
highspeed analogtodigital converters.
Accordingly, extensive research is being conducted
to develop novel architectures, circuit configurations,
layouts, design styles, and design methodologies with
the aim of improving adder speed and energy effi
ciency [4, 7–10].
This paper deals with ripplecarry full adders 
implemented in complementary metal–oxide–semi
conductor (CMOS) technology, whose advantages
include zero static power consumption and freedom
from fractional voltage levels at the internal nodes (no
voltage recovery is needed). A new CMOS circuit
implementation of a onebit adder cell is proposed
that should enable one to achieve the highest speed
among the adders concerned. Comparisons are made
with some fulladder cells in common use.
2. ADDER PERFORMANCE PARAMETERS
The most useful performance parameters of an
adder seem to be delay and power consumption .
A third parameter known as power–delay product
(PDP) is becoming increasingly popular for compar
ing different adder designs [3, 11–14].
The maximum delay
carry full adder may be written as
is the delay due to carry generation and prop
agation from input to output .
The maximum delay refers to the worst case where
a carry is generated for every bit, as Fig. 1 illustrates.
Equation (1) is only an approximation in that it
neglects the delay
associated with the addition of
the carry generated at the most significant bit and the
result of addition at the same bit.
Taking this into account leads to
decreases steadily with
, lying under 0.1 for
= 8, Eq. (2) should
be used instead of Eq. (1) when accurately comparing
For static CMOS digital circuits, the total power
is in general given by
is the dynamic power consumption, i.e.,
the power consumed due to switching during node
is the power consumption
associated with transistor leakage under cutoff condi
is the power consumption of a short
circuited logic gate; and
is the power consumption
associated with using voltage levels that are fractions of
the supply voltage.
total dynamic leakage shortcircuit DC
,PP P P P
New CMOS Circuit Implementation of a OneBit FullAdder Cell
V. V. Shubin
SemiconductorDevice and Microelectronics Department, Novosibirsk State Technical University, Novosibirsk, Russia
Received March 4, 2010
—A new mirror CMOS circuit implementation of a onebit fulladder cell is proposed. Using
CMOS technology provides zero static power consumption and the freedom from fractional voltage levels at
the internal nodes (no voltage recovery is needed). The solution proposed is shown to be superior in carry
speed to any alternative CMOS implementation reported so far, and should therefore be suitable for building
highspeed multibit adders.