The physical principles are considered of on-chip interconnection degeneration and failure in sub-1-µm technologies from the viewpoint of multilevel-metallization reliability. A general theory and simulation results are presented that deal with electromigration-induced failure of thin-film conducting tracks on the micro- and nanometer scales. They provide a detailed treatment of micro-, meso-, and nanoscopic mechanisms underlying the deformation and breaking of actual interconnection configurations. Parts 1 and 2 contain (i) the derivation and analysis of basic kinetic equations; (ii) the formulation and solution of three-dimensional boundary-value problems representing the transport of vacancies (both in the bulk and along grain boundaries) and the development of deformation and stress; (iii) models of void nucleation and development; (iv) an analysis of a multilevel-metallization lifetime; and (v) the identification of potential break locations in a multilevel metallization in relation to current density, metallization structure and layout, temperature, and the grain structure of the conducting material. Part 3 deals with electromigration in doped on-chip polycrystalline interconnections in terms of lengthening their lifetime. To predict electromigration resistance, models are constructed that represent the influence of texture and other grain-boundary properties on the effective charges of native and dopant ions.
Russian Microelectronics – Springer Journals
Published: Nov 15, 2009
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