Monitorability for the Hennessy–Milner logic with recursion

Monitorability for the Hennessy–Milner logic with recursion We study $$\mu $$ μ HML, a branching-time logic with least and greatest fixpoints, from a runtime verification perspective. The logic may be used to specify properties of programs whose behaviour may be expressed as a labelled transition system. We establish which subset of this logic can be monitored for at runtime by merely observing the runtime execution of a program. A monitor-synthesis algorithm is defined for this subset, where it is shown that the resulting synthesised monitors correctly perform the required analysis from the observed behaviour. We also prove completeness results wrt. this logical subset that show that, up to logical equivalence, no other properties apart from those identified can be monitored for and verified at runtime. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Formal Methods in System Design Springer Journals

Monitorability for the Hennessy–Milner logic with recursion

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Publisher
Springer US
Copyright
Copyright © 2017 by Springer Science+Business Media New York
Subject
Engineering; Circuits and Systems; Electrical Engineering; Computer-Aided Engineering (CAD, CAE) and Design; Software Engineering/Programming and Operating Systems
ISSN
0925-9856
eISSN
1572-8102
D.O.I.
10.1007/s10703-017-0273-z
Publisher site
See Article on Publisher Site

Abstract

We study $$\mu $$ μ HML, a branching-time logic with least and greatest fixpoints, from a runtime verification perspective. The logic may be used to specify properties of programs whose behaviour may be expressed as a labelled transition system. We establish which subset of this logic can be monitored for at runtime by merely observing the runtime execution of a program. A monitor-synthesis algorithm is defined for this subset, where it is shown that the resulting synthesised monitors correctly perform the required analysis from the observed behaviour. We also prove completeness results wrt. this logical subset that show that, up to logical equivalence, no other properties apart from those identified can be monitored for and verified at runtime.

Journal

Formal Methods in System DesignSpringer Journals

Published: Mar 24, 2017

References

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