Microwave-Assisted Size Control of Colloidal Nickel
Nanocrystals for Colloidal Nanocrystals-Based Non-volatile
Memory Devices
MANOJ YADAV,
1
RAVI SHANKAR R. VELAMPATI,
2
D. MANDAL,
3
and ROHIT SHARMA
1,4
1.—Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar,
PB 140001, India. 2.—Semi-Conductor Laboratory, Department of Space, Government of India,
Mohali, PB 160071, India. 3.—Department of Chemistry, Indian Institute of Technology Ropar,
Rupnagar, PB 140001, India. 4.—e-mail: rohit@iitrpr.ac.in
Colloidal synthesis and size control of nickel (Ni) nanocrystals (NCs) below
10 nm are reported using a microwave synthesis method. The synthesised
colloidal NCs have been characterized using x-ray diffraction, transmission
electron microscopy (TEM) and dynamic light scattering (DLS). XRD analysis
highlights the face centred cubic crystal structure of synthesised NCs. The
size of NCs observed using TEM and DLS have a distribution between 2.6 nm
and 10 nm. Furthermore, atomic force microscopy analysis of spin-coated NCs
over a silicon dioxide surface has been carried out to identify an optimum spin
condition that can be used for the fabrication of a metal oxide semiconductor
(MOS) non-volatile memory (NVM) capacitor. Subsequently, the fabrication of
a MOS NVM capacitor is reported to demonstrate the potential application of
colloidal synthesized Ni NCs in NVM devices. We also report the capacitance–
voltage (C–V) and capacitance–time (C–t) response of the fabricated MOS
NVM capacitor. The C–V and C–t characteristics depict a large flat band
voltage shift (V
FB
) and high retention time, respectively, which indicate that
colloidal Ni NCs are excellent candidates for applications in next-generation
NVM devices.
Key words: Nanocrystals (NCs)-based non-volatile memory (NVM), XRD,
TEM, DLS, spin-coating, AFM, fabrication and characterization,
flat band voltage shift (V
FB
)
INTRODUCTION
The concept of discrete semiconductor nanocrys-
tals (NCs)-based non-volatile memory (NVM) was
first reported in Ref. 1. Since then, there have been
many efforts to optimize the performance of discrete
NCs-based NVM devices. There are a number of
emerging NVM devices
2
that include phase change
memory,
3
ferroelectric random-access memory,
4
resistive random-access memory,
5,6
spin torque
transfer random-access memory
7
and NCs-based
NVM.
8–11
Of these, NCs-based NVM is most com-
patible with complementary metal oxide semicon-
ductor (CMOS) integrated circuit technology, as it
demonstrates the lowest cell sizes that result in low-
cost and reduced power dissipation. A simplified
schematic of a NCs-based NVM device is shown in
Fig. 1.
Scaling of NVM devices is quite critical, as per the
international technology roadmap for semiconduc-
tors predictions.
12
Recently, two-dimensional (2D)
materials like graphene have been investigated for
applications in NVM devices.
13
However, due to a
continuous floating gate layer and an equivalent
work function of the graphene and silicon substrate,
graphene-based NVM devices are prone to charge-
(Received August 22, 2017; accepted March 2, 2018;
published online March 13, 2018)
Journal of ELECTRONIC MATERIALS, Vol. 47, No. 7, 2018
https://doi.org/10.1007/s11664-018-6200-2
Ó
2018 The Minerals, Metals & Materials Society
3560
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