The problems of simulation and characterization of VLSI standard cell libraries designed on the basis of semiconducting CMOS-technologies of the deep submicron and nanometer level are considered. The acceleration methods of the characterization process resulted in the identification of parameters of logic cell macromodels under the multiple simulation of cells on a circuit level for different versions of input actions and under the values of process-dependent parameters and modes of circuit operation. The algorithms of constructing the circuit characterization are directed at decreasing computational expenditures and ensuring the required accuracy of the macromodels. The results of the comparative analysis of different versions of the proposed algorithms are given.
Russian Microelectronics – Springer Journals
Published: Dec 4, 2011
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