A method and algorithm for accelerating the simulation in the route of the joint hardware-software verification of Multicore systems-on-chip (SoC) are developed. An approach with the peculiarity of simulating the asymmetric memory access, which provides the solution for the synchronization problem in multiprocessor systems with a considerable increase in performance as compared to the simulation of the RTL model, is proposed.
Russian Microelectronics – Springer Journals
Published: Nov 14, 2014
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