ISSN 10637397, Russian Microelectronics, 2014, Vol. 43, No. 7, pp. 501–504. © Pleiades Publishing, Ltd., 2014.
Original Russian Text © A.V. Zaikin, 2013, published in Izvestiya Vysshikh Uchebnykh Zavedenii. Elektronika, 2013, No. 4(102), pp. 32–37.
The more severe requirements for the parameters
of produced circuits, specifically, the operating speed,
the power consumption, the occupied area, and the
yield, stimulate the development of submicron tech
nologies and nanotechnologies. By this means, the
methods and models used in CAD become inopera
tive. Thus, the summary length of conductors is no
longer the governing placementquality index. If the
summary length of conductors is reduced, then the
traceability inevitably falls; this has an adverse effect
on the quality parameters of a circuit and increases the
engineering time. In moving to processes with design
rules that propose norms less than 100 nm, the influ
ence of parasitic actions (cross talk and the IR drop)
on the operating capacity of circuits also grows; there
fore, it is necessary to take such actions into account at
the early design phases and introduce new criteria. In
this respect it is important to elaborate new fast meth
ods for synthesizing, which allow the number of crite
ria to be easily increased.
In automating the topological layout design, two
main approaches to the problem of taking into
account the number of criteria (multicriteria optimi
zation) are employed: (1) the use of a weighting goal
function  and (2) the sequential optimization for
prioritized criteria . The quality of the solutions
obtained on taking the first approach depends on the
architecture of the designed VLSI circuit, while taking
the second one often leads to a local optimum.
The proposed approach consists in employing not
only the ultimate results implemented by iterative
algorithms of optimization for one of the criteria but
also the preliminary results. This permits optimizing a
number of criteria. The placement algorithm is pre
sented in Fig. 1. The idea of this approach resembles
the idea described in , where families of Steiner
trees are constructed.
PLACEMENT METHOD WITH ALLOWANCE
FOR A NUMBER OF CRITERIA
For each criterion an iterative optimization algo
rithm with a corresponding goal function is chosen.
The algorithm is activated with an arbitrary initial
placement of the standard cells at the input. In opera
tion the algorithm moves the cells; in this case, prelim
inary solutions are generated.
The preliminary solutions are saved. Upon com
pletion of the algorithm’s operation, for each cell the
path of its motion during the iteration is constructed;
this is the history of motion transformed into a motion
map, so that the intensity of the pixels of a decision
map depicts the number of iterations in which a par
ticular cell took a particular location. Hence, at the
output of an algorithm of optimization for one of the
criteria a set of motion maps of cells is obtained.
As soon as the sets of motion maps are obtained for
each criterion, we can go to the stage of finding a ter
minal decision (coordinates in the placement space)
for each cell. To this end, from each set of maps, we
choose maps conforming to a cell, for which the solu
tion is found, and their superposition is performed.
The core of superimposing decision maps is in finding
the intersection of the intensity areas of the maps. The
proposed method is based on the assumption that an
input criterion has a direct proportional influence on
the intensity of each point of a decision map. Hence,
if the point of the maximum intensity among points
from the intersection of intensity areas of maps con
structed with allowance for various criteria is chosen,
this means that we choose a solution maximally com
plying with the input criteria.
If the solution is not obtained (this can take place if
the intersection of intensity areas is not found), one of
the decision maps is fuzzified to enlarge the intensity
areas and superimposing is repeated.
Method for Placing Standard VLSI Cells, Based on Combining
the Results of Operation of Iterative Algorithms
A. V. Zaikin
National Research University of Electronic Technology MIET, proezd 4806 5, Zelenograd, Moscow, 124498 Russia
Received October 10, 2012
—The new approach to solving the problem of global placement of standard VLSI cells is proposed.
The notion of the history of the motion of a cell is introduced and the algorithm of getting motion maps is
given. The original algorithm of synthesizing a placement by combining motion maps is described.