ISSN 1063-7397, Russian Microelectronics, 2008, Vol. 37, No. 1, pp. 62–71. © Pleiades Publishing, Ltd., 2008.
Original Russian Text © G.G. Davydov, A.V. Sogoyan, A.Y. Nikiforov, A.V. Kirgizova, A.G. Petrov, A.Y. Sedakov,
I.B. Yashanin, 2008, published in Mikroelektronika, 2008, Vol. 37,
No. 1, pp. 67–77.
Large-scale integration (LSI) circuits realized in
complementary metal–oxide–semiconductor (CMOS)
technology, whether bulk or epitaxial, are unlikely to
meet the standard requirements for pulsed-radiation
performance under which the worst-case radiation
hardness must be
and the upset immu-
nity must be greater than
, or even equal to
in some cases. The problem can be solved by dielec-
tric isolation of the circuit elements to considerably
reduce photocurrents and to suppress parasitic cross
coupling that results from pulsed irradiation. Examples
of this strategy are provided by the silicon-on-insulator
(SOI) technology in general and its silicon-on-sapphire
(SOS) version in particular, the latter being adopted by
Russia’s electronic industry.
CMOS circuits implemented by SOS technology
differ from bulk ones in two respects (Fig. 1):
(i) Radiation-induced latchup is impossible.
(ii) Individual circuit elements are formed in a thin
silicon layer in a top-down fashion .
On the other hand, there is a lattice mismatch
between the silicon and the sapphire, the Si and Al
 lattice spacings being 5.43 and 5.16 Å, respec-
tively. Small as it may appear, the mismatch produces
lattice defects at the interface that act as hole trapping
centers when the circuit is exposed to ionizing radiation
. The resulting accumulation of radiation-induced
charge leads to increased leakage currents and, there-
fore, to a growth in standby current.
Due to a random manner in which lattice defects are
scattered over the Si/Al
interface , items of a
given SOS circuit should display a considerable spread
in radiation performance, particularly standby current
. Indeed, this parameter has been found to vary by an
order of magnitude over an irradiated batch of circuits
made in Russia (Fig. 2a). Moreover, the distribution of
standby current may not be unimodal (Fig. 2b), a fact
Method for Online Nondestructive Hardness Assurance
for CMOS LSI Circuits Realized in SOS Technology
G. G. Davydov, A. V. Sogoyan, A. Y. Nikiforov, A. V. Kirgizova, A. G. Petrov,
A. Y. Sedakov, and I. B. Yashanin
Specialized Electronic Systems (SPELS), Moscow, Russia
Received April 9, 2007
—The radiation performance of digital CMOS circuits realized in SOS technology is investigated in
relation to the radiation-induced charge at the silicon–sapphire interface. A nondestructive hardness-assurance
method based on radiation annealing is proposed, and reasons are given why this approach should be feasible.
The limits of applicability of the method are assessed.
PACS numbers: 85.40.-e
METHODS AND RESULTS