Low-Latency CRC Calculation in Turbo-Code Decoding

Low-Latency CRC Calculation in Turbo-Code Decoding Design of Turbo-Code decoders for the 3GPP LTE/LTE-A standard focuses on achieving a high-throughput of up to 1 Gbps with low decoding latencies at very high code rates. At code rates close to one, as specified in LTE/LTE-A, the decoding process can oscillate. Although the decoder converges to a valid code word after half-iteration i, after half-iteration $$i+1$$ i + 1 the decoded code word is invalid again. To circumvent this, the CRC that is attached to each code word must be evaluated after each half-iteration. We present a generalized architecture for calculating the CRC On-the-fly during both non-interleaved and interleaved half-iterations and thus explicitly taking into account the requirements for low-latency Turbo-Code decoding. Further, we investigate the latency-, and energy savings provided by employing this calculation scheme. Lastly, we give post layout synthesis results for a case study implementation in state-of-the-art 28 nm FDSOI technology. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png International Journal of Wireless Information Networks Springer Journals

Low-Latency CRC Calculation in Turbo-Code Decoding

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Publisher
Springer Journals
Copyright
Copyright © 2017 by Springer Science+Business Media, LLC
Subject
Engineering; Electrical Engineering
ISSN
1068-9605
eISSN
1572-8129
D.O.I.
10.1007/s10776-017-0374-z
Publisher site
See Article on Publisher Site

Abstract

Design of Turbo-Code decoders for the 3GPP LTE/LTE-A standard focuses on achieving a high-throughput of up to 1 Gbps with low decoding latencies at very high code rates. At code rates close to one, as specified in LTE/LTE-A, the decoding process can oscillate. Although the decoder converges to a valid code word after half-iteration i, after half-iteration $$i+1$$ i + 1 the decoded code word is invalid again. To circumvent this, the CRC that is attached to each code word must be evaluated after each half-iteration. We present a generalized architecture for calculating the CRC On-the-fly during both non-interleaved and interleaved half-iterations and thus explicitly taking into account the requirements for low-latency Turbo-Code decoding. Further, we investigate the latency-, and energy savings provided by employing this calculation scheme. Lastly, we give post layout synthesis results for a case study implementation in state-of-the-art 28 nm FDSOI technology.

Journal

International Journal of Wireless Information NetworksSpringer Journals

Published: Oct 13, 2017

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