1063-7397/05/3406- © 2005 MAIK “Nauka /Interperiodica”
Russian Microelectronics, Vol. 34, No. 6, 2005, pp. 397–406. Translated from Mikroelektronika, Vol. 34, No. 6, 2005, pp. 466–477.
Original Russian Text Copyright © 2005 by Bibilo.
Although it was originally intended for the simula-
tion of already designed circuits, Very High Speed Inte-
grated Circuits Hardware Description Language
(VHDL) has found application in the synthesis of logic
networks from behavioral descriptions. In fact, it has
become an international standard and an input language
of many industrial computer-aided-design (CAD) tools
for custom, semicustom, and programmable logic inte-
grated circuits (ICs).
LeonardoSpectrum, or simply Leonardo, is one of
the more popular VHDL synthesizers for ﬁeld-pro-
grammable gate arrays (FPGAs), complex programma-
ble logic devices (CPLDs), and very-large-scale-inte-
gration (VLSI) application-speciﬁc ICs (ASICs). With
ASICs, a user-deﬁned library of logic elements can be
employed. This feature, which sets Leonardo apart
from other synthesizers, makes it suitable for the con-
version of programmable logic into designs based on
domestic gate arrays . Leonardo can also work with
the Verilog language.
This paper outlines the methodological framework
of Leonardo and gives practical examples to illustrate
the interconversion of designs made in a user-deﬁned
library and ones based on programmable logic arrays
(PLAs) by the combined use of Leonardo and Custom
Logic, a Belarussian toolkit for the design of VLSI cus-
tom control logic . It is desirable that the reader have
a basic familiarity with VHDL.
SYNTHESIS GOAL AND STAGES
For a discrete device the goal of synthesis is to
implement a given functional speciﬁcation
in a logic
from a given set
of logic elements.
For combinational logic a functional speciﬁcation is
a set of Boolean functions
Synthesis is commonly performed in three stages .
Stage 1 is the conversion of the functional speciﬁca-
tion into a register-transfer-level (RTL) description.
An RTL description is a mixed representation in
which memory elements (ﬂip-ﬂops) are represented in
structural terms (as building blocks and their intercon-
nections) whereas combinational elements are repre-
sented as Boolean equations. An RTL description can
also be formulated in VHDL, in which case the combi-
national elements are described by signal assignment
statements (the data ﬂow style), and the memory ele-
ments are represented as component instantiation state-
Stage 2 is technology-independent optimization,
which deals with a two- or multiple-level Boolean rep-
resentation of the combinational logic.
Stage 3 is technology mapping, i.e., the conversion
of the optimized Boolean representation into a network
of logic elements from the set
Stages 2 and 3 are commonly grouped under the
The stepwise approach is invari-
ably followed by VHDL synthesizers due to the com-
plexity of the task.
SYNTHESIZABLE SUBSET OF VHDL
A functional speciﬁcation must be written within a
subset of VHDL speciﬁc to the synthesizer employed;
it will be referred to as the synthesizable subset . A
signiﬁcant advantage of Leonardo is that it accepts a
considerably larger part of VHDL than other synthesiz-
ers; details can be found in . Obviously, a speciﬁca-
tion in VHDL must be tested for correctness before
being fed to a synthesizer.
Since the signals in a ﬁnal logic network are repre-
sented as bits, synthesis from a VHDL speciﬁcation
involves conversion of original signal types into the
VHDL types std_logic and std_logic_vector. The con-
version rules of Leonardo are given in Table 1.
Logic Synthesis from VHDL Descriptions Using
LeonardoSpectrum: Theoretical Basis
P. N. Bibilo
Joint Institute of Problems of Information Science, National Academy of Sciences of Belarus, Minsk, Belarus
Received December 8, 2004
—An overview is given of the methodological framework of LeonardoSpectrum, a VHDL synthesis
tool. Its use in conjunction with Custom Logic is discussed in the context of VLSI logic synthesis.