Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration

Investigation of the impact of plasma etching steps on the roughness of the fin FET channel... The origin of the roughness of Fin FET channel sidewalls in the heterointegration scheme was discussed. It is shown that its presence is caused by the original roughness of the Si sidewalls of the “fin” structures formed during plasma etching. A number of processing steps affecting the morphology of the Si fin structures were analyzed. The smoothing of the resistive polymeric mask in the HBr-containing plasma, distributed trimming in the layered mask, and control of the temperature conditions are among these technologies. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Russian Microelectronics Springer Journals

Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration

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Publisher
Pleiades Publishing
Copyright
Copyright © 2016 by Pleiades Publishing, Ltd.
Subject
Engineering; Electrical Engineering
ISSN
1063-7397
eISSN
1608-3415
D.O.I.
10.1134/S1063739716030033
Publisher site
See Article on Publisher Site

Abstract

The origin of the roughness of Fin FET channel sidewalls in the heterointegration scheme was discussed. It is shown that its presence is caused by the original roughness of the Si sidewalls of the “fin” structures formed during plasma etching. A number of processing steps affecting the morphology of the Si fin structures were analyzed. The smoothing of the resistive polymeric mask in the HBr-containing plasma, distributed trimming in the layered mask, and control of the temperature conditions are among these technologies.

Journal

Russian MicroelectronicsSpringer Journals

Published: May 19, 2016

References

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